Blog Review: May 3

AI chips drive design exploration; hierarchy in custom design; power module current density; DPU adoption.


Synopsys’ Thomas Andersen considers the requirements of AI-optimized chips that are resulting in exploration of different memory configurations, different types of memory, and different types of processor technologies and software components.

Cadence’s Girish Vaidyanathan considers the role of hierarchy and partitioning in custom design and looks at how a virtual hierarchy allows layout designers to choose a design hierarchy different from the logical design hierarchy.

Siemens’ Wilfried Wessel answers five common questions about power module current density and its role in determining module efficiency and performance.

Arm’s Marc Meunier introduces the Open Programmable Infrastructure project, which is focused on utilizing open software and standards, as well as frameworks and toolkits, to enable the rapid adoption of data processing units (DPUs).

Ansys’ Akanksha Soni examines the causes behind electromagnetic coupling and key techniques for mitigating its effects.

Infineon’s Danie Schneider notes that for a smart factory to function, huge amounts of data are collected, transmitted, analyzed and processed in all areas of production.

In a blog for SEMI, Edwards Vacuum’s Chris Jones considers the actions needed to reach net-zero emissions by 2050.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey asks if reuse, which is now a staple for the semiconductor design industry, is ready to use RTL generated by AI.

Synopsys’ Samad Parekh and Noman Hai look at design tradeoffs in the choice of multiplexer architecture, equalizer design, serialization technique, and output driver.

Expedera’s Paul Karazuba warns that although CIM can speed up multiplication operations, it comes with added risk and complexity.

Movellus’ Barry Pangrle looks at what’s in TSMC’s roadmap for ramping new processes and packaging.

National Instruments’ Chen Chang and Alejandro Escobar Calderon explain why carriers are turning their focus to 5G mmWave alternatives.

Keysight’s Jenn Mullen calls for automotive testing methods that keep up with the rapid iterations inherent in the software space.

Codasip’s Tora Fridholm recounts the building of a chip for event-based vision, inspired by the detection of light in the eyes and the processing of visual information in the brain.

Siemens EDA’s Hossam Sarhan and Alexandre Arriordaz spell out why waiting until signoff to verify reliability compliance is no longer a practical or realistic option.

Renesas’ Eldar Sido presents the benefits of a micro-architecture extension to replace lower to mid-tier DSP cores with on-chip processing.

Cadence’s Paul McLellan points to keynotes that highlighted AI and data center communications.

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