Blog Review: May 3

Computing assumptions; HDMI 2.1; OPC; GF’s Fab 8; buffer chips in data centers; quantum computing.

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Cadence’s Paul McLellan shares highlights from a recent IRDS panel, including changing the assumptions about computing and looking for the next “killer app.”

Synopsys’ Meenakshy Ramachandran introduces the array of improvements in HDMI 2.1, from higher bandwidth to Dynamic HDR.

Mentor’s Minghui Fan checks out advancements in optical proximity correction and resolution enhancement technology.

In a video interview, GlobalFoundries’ Tom Caulfield chats with VLSI Research CEO G. Dan Hutcheson about fab management, the difficulties of bringing up a greenfield fab, and the IBM Microelectronics acquisition.

Rambus’ Aharon Etengoff focuses on the role of buffer chips in the data center as processor and memory requirements change with the shift from PC-centric to cloud-based computing.

Intel’s Ron Wilson dives into quantum computing with an accessible discussion of what it is and the questions surrounding its actual practicality.

Marvell’s Nick Ilyadis runs through the top trends in data centers as they try to keep up with the demand for higher and higher bandwidth.

ARM’s Eoin McCann asks Soshun Arai of ARM and Mark Sykes of Recognition Technologies about the current state of voice recognition and infotainment in cars.

NI’s James Kimery argues that as 5G standardization moves forward, mmWave channel measurement is crucial.

Lam CEO Martin Anstice discusses the broad trends driving demand for semiconductors and the sustainability of innovation in a CNBC video.

Ansys’ Sandeep Sovani highlights an Elon Musk talk about his vision of revolutionizing transportation.

Icon Labs’ Alan Grau notes that lax security for IoT devices is leading to a rise in cyber-vigilantism.

NXP’s Esther Chang highlights how China plans to use technology to reduce traffic jams and pollution.

In a video, Cadence’s Megha Daga takes a look at the compute requirements and memory bandwidth challenges that face convolutional neural networks.

Plus, check out the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling finds that after decades of failing to live up to expectations, massively parallel systems finally are getting serious attention.

Technology Editor Brian Bailey argues that it’s our own fault so little research is being conducted in EDA.

Mentor’s Mike Santarini questions whether there is a better way to predict growth for individual segments than industry-wide forecasts.

OneSpin’s Dave Kelf contends that it’s time to leverage comprehensive assertion-based verification.

Synopsys’ Malte Doerper points to the benefits of virtual prototyping for SSD and NAND controller software development.

Cadence’s Frank Schirrmeister provides examples of the next productivity leap in verification.

eSilicon’s Mike Gianfagna compares 2.5D design to the first trips in space.

Aldec’s Krzystof Szcur examines software as a way of driving design under test on an FPGA prototyping platform.