Blog Review: Nov. 20

Arm’s Ben Fletcher points to research into a new low-cost alternative to through-silicon vias in 3D stacked ICs, particularly cost-sensitive IoT designs, where communication between silicon layers is completely wireless.

Cadence’s Paul McLellan checks in on the progress of DARPA’s OpenROAD project to build a no-human-in-the-loop open source EDA flow for leading-edge nodes.

Mentor’s Colin Walls shares a few more tips for embedded software development with some things to pay careful attention to when using C/C++.

A Synopsys writer explains the new features and latency optimization techniques available in AMBA5 CHI Issue D, including memory system resource partitioning and monitoring and inference parity protection for functional safety.

VLSI Research’s Dan Hutcheson chats with Aki Fujimura of D2S about what the eBeam Initiative found in this year’s semiconductor mask making survey.

ANSYS’ Curt Chan considers using reverse engineering to replicate parts that are no longer available, the legality of different situations, and how 3D scan-to-CAD and additive manufacturing make it possible.

Applied Materials’ Steve Ghanayem introduces a new collaborative lab for prototyping of new chip materials, process technologies and devices at the State University of New York Polytechnic Institute.

Plus, check out the highlighted blogs from last week’s Low Power—High Performance newsletter:

Editor In Chief Ed Sperling contends that while AI can speed up chips, it’s not always obvious where and for how long.

Fraunhofer EAS’s Roland Jancke finds that improved quality begins with the combination of different models and previously separated domains into a comprehensive virtual design platform.

Rambus’ Frank Ferro describes balancing tradeoffs between bandwidth, capacity and power-efficiency.

Mentor’s Chris Kwok, Priya Viswanathan, and Ping Yeung explain how hard-to-catch reset bugs call for static analysis, simulation, and formal analysis used in concert.

Synopsys’ Pieter van der Wolf and Dmitry Zakharov lay out what’s needed for performing inference efficiently in low/mid-end edge devices.

Arm’s Steve Roddy argues that we need to design systems capable of dynamically adjusting the type—not just the speed—of processing resource they can deliver.

Moortec’s Stephen Crosher sketches out important considerations to make when determining where to place thermal monitoring sensors on a chip.

Adesto’s Jen Bernier-Santarini says creating a campus-wide access system can mean managing hundreds of devices networked together.