Blog Review: Nov. 9

Cadence’s Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built.

Synopsys’ Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specification, including a doubling of the bandwidth per lane, PAM 3 encoding, four protocols on one bus, asymmetric mode for applications where most of the data is being transmitted out of the host computer versus data received, and direct connect mode for future USB-C peripherals.

Siemens EDA’s Chris Spear looks at the different flavors of UVM and why the choice of version, how you define the behavior of your sequence item classes, how your sequence talks to the driver, and when the component executes is important.

Arm’s Sam Taylor introduces the new PSA Certified Firmware Update API to provide a standard way of supporting firmware updates for IoT devices and create a basic mechanism on the device that the ecosystem can rely on to ensure a firmware image is applied securely.

Coventor’s Sumant Sarkar creates a model of an airgap created between the gate and source/drain to investigate the impact on reducing parasitic capacitance.

Ansys’ Kerry Herbert introduces several of the sampling schemes and algorithms that are used to measure Modulation Transfer Function (MTF) and capture the performance aspects of an optical system.

SEMI’s Jaegwan Shim shares updates from the semiconductor industry in Korea, including the impact of the global economy, Covid-19, and workforce development initiatives.

Nvidia’s Paraskevas Bakopoulos and Elad Mentovich explain a recently-completed project that explored ferroelectric materials to improve performance and reliability in very high-speed silicon nanophotonics and plasmonics.

Memory analyst Jim Handy takes a look back at the history of NAND memories prior to NAND flash and learns that certain advances were made much earlier than flash’s commercial success.

Intel’s Vishnu Madhu points to efforts towards more sustainable compute, particularly how incremental innovations to machine learning deployment could reduce energy usage while not requiring a complete overhaul of your pipeline.

NXP’s Timo van Roermund discusses the UN R155 and ISO/SAE 21434 automotive cybersecurity mandates and why collaboration is essential to overcome the issues automakers and supplies will face in meeting them.

Plus, don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Rambus’ Marcel van Loon warns that connected devices contain a wealth of information that is of great interest to attackers.

Siemens EDA’s Jacob Wiltgen and Patmos Engineering Services’ Michelle Lange and Tammy Reeve explain how to ensure tools can perform a design or verification activity to an acceptable level of confidence.

Riscure’s Jasper van Woudenberg highlights research from the Black Hat conference about a side-channel attack on a Starlink terminal.

Arteris IP’s Frank Schirrmeister makes sense of the many automotive safety standards and requirements.

Cadence’s Steve Brown finds no signs of a RISC-V adoption slowdown, from deeply embedded to HPC.

Infineon’s Danie Schneider says smart buildings depend on the ability to understand who is in a space and how they move.

Synopsys’ Dana Neustadter looks at how high-performance, low-latency memory encryption preserves performance while protecting data.

Onto Innovation’s John Chang, Corey Shay, James Webb, and Timothy Chang lay out why chiplets will require increasingly larger packages and more redistribution layers.

Siemens’ Jayant D’Souza describes how using reverse scan chain diagnosis accelerates yield ramp.

Synopsys’ Pawini Mahajan looks at making product development and deployment more deterministic.

CyberOptics’ Subodh Kulkarni summarizes the challenges in using traditional methods for measuring uniformity.

Teradyne’s Richard Fanning and John Rowe present small improvements in any test step that can reduce overall cycle time.