How To Improve Yield Ramp For New Designs And Technology Nodes

Using reverse scan chain diagnosis accelerates yield ramp so chip makers can meet market windows.


The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification using test chips, scan chain failures account for most of the chip failures. Diagnosing those scan chain defects is a powerful way to uncover new and systematic defects.

The chip maker’s goal is to get through technology qualification, then product qualification, to entitlement yield as quickly as possible. In each of these phases, scan chain diagnosis and electrical fault isolation (EFI) are employed to pinpoint the location of the defect and determine a root cause.

What is scan chain diagnosis?

Scan chains enable scan testing of digital ICs, but these scan chains themselves must be validated. Typically chain diagnosis requires both failing chain test patterns and failing scan patterns. The diagnosis process is a two-step process:

  1. The failing chain(s) and the defect type is identified. The location of the defect could be anywhere in the entire range of scan cells in the defective scan chain.
  2. The failing scan patterns are used to determine the possible suspect scan cells in the failing chain that could contain the defect.

Scan chains typically allow the shifting of data in a single direction. However, with a reversible chain technology, the scan chains are designed so that they can shift in the reverse direction as well. Figure 1 illustrates the construction of the scan chains for bi- directional shifting. The direction is controlled by a direction control pin (DIR).

Fig. 1: Scan chains for bi-directional shifting.

What is reversible chain diagnosis?

With reversible chain hardware, chain test patterns can be generated for each of the directions of data shift in the scan chains. This bidirectionality of the scan chains and the patterns is then used by chain diagnosis, with significant advantages over the traditional flow.

How does it work? To illustrate, assume that a single permanent defect exists on cell 2 of a scan chain that behaves like a stuck-at 0 fault (SA0). The diagnosis occurs in 4 steps as follows:

In steps 1 and 2, we load the data 111111 from left to right and unload this data from right to left, as shown in figure 2. Due to the defect at cell 2, the unloaded data is 111000.

Fig. 2: Steps 1 and 2 of reversible scan chain diagnosis.

In steps 3 and 4, the same pattern data, 111111, is loaded from right to left and unloaded from left to right. Due to the defect at cell 2, the unloaded data is 110000 after Step 4.

Fig. 3: Steps 3 and 4 of reversible scan chain diagnosis.

The cell position 2 shows the same difference in both directions, indicating the defect location.

The advantage of this method is that only chain test patterns are required for diagnosis, not failing scan patterns. Since only failing chain test patterns are required, the diagnosis process runs much faster.

What are the setup costs of reversible chain diagnosis?

Using reversible chain diagnosis requires some changes to the design hardware and the design flow. The scan chains have to be stitched in a manner that accomplishes shifting in either direction, which can be done in a variety of ways. One method that leaves the regular design flow untouched is illustrated in figure 4.

Fig. 4: Design flow for reversible scan chain diagnosis.

In this ECO-based flow, the reversible scan path is added to the final netlist using ECO scripts in the place and route (PNR) tool. The rest of the flow proceeds as usual, for example, chain patterns are generated by the ATPG tool automatically for both directions. Scan path reports, ATE fail log, the flat model, and patterns are given to the diagnosis software to produce a chain diagnosis result.

What’s the benefit of reversible chain technology on chain diagnosis?

Reversible chain technology has a large positive impact on chain diagnosis. We performed injection experiments on two designs, each with 100 failure files created by injecting defects at randomly selected scan cells using a simulator. Volume diagnosis was performed on all 100 failure files for each design. For all injected defects (and defect types), the reversible scan chain methodology reported a single suspect per diagnosis report.

We also used an additional metric called defect enclosing circle ratio (DECR) to compare the results between baseline and reversible scan chain diagnosis. DECR, illustrated in figure 5, is defined as the ratio between the diameters of the enclosing circles for the reversible chain diagnosis results and the baseline chain diagnosis results.

Fig. 5: Defect enclosing circle ratio.

The DECR for the reversible chain diagnosis suspects was at least 2X smaller for at least 80% of the diagnosis reports. This reduction has a direct implication on the area to be analyzed by fault isolation (FI) and physical failure analysis (PFA).

And when reversible chain diagnosis was performed on a test chip on a leading-edge technology node, results showed ~4x better resolution and a 4x improvement in run time.

Improving yield ramp for new designs and technology nodes is an economic imperative. Leveraging reversible scan chain architecture improves scan chain diagnosis, accelerating yield ramp so chip makers can meet their market window.

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