Blog Review: Oct. 15

Obesity makes your liver age faster, but you’ll need a sophisticated biological clock to see that. Ansys’ Bill Vandermark uncovers the top 5 engineering articles of the week. This one includes cyborg horses and an implanted prosthetic arm.

Mentor’s Colin Walls takes a look at “hard” and “soft” real time. It sounds like something out of a Salvador Dali painting.

Rambus’ Aharon Etengoff takes us inside the next-gen server architectures—80 cores, most data on flash and new NVM—but the fundamental shift is from software-defined to software-based.

Cadence’s Brian Fuller reports on a speech by Wired editor Chris Anderson, who contends there is a new industrial revolution dawning in electronics. This is the kind of prediction that’s worth revisiting in 5 or 10 years.

Synopsys’ Marc Greenberg has found the DDR4 datasheets from Micron, Samsung and SK Hynix. DDR4 is here, but you’ll need to plan for it.

How do you reduce engine emissions? Part of the solution is electronic. ARM’s Juergen Jagst looks at regulations around the world and what new powertrain requirement will foster.

A different tack for the same emissions problem is in the area of ultra clean combustion. Ansys’ Hossam El-Asrag sheds some light on a difficult mechanical engineering issue.

Verification expert Gaurav Jalan points the way toward context-aware verification, which is essential with flexible IP. This should add a new wrinkle into the verification experience.

ARM’s Tom Stevens points to an article about how to design chips with hundreds or thousands of cores. This is all good news for EDA.

Cadence’s Axel Scherer finds there is still a use for old technology and spinning media. Good music never dies—especially when your kids start demanding it.

Synopsys’ Mick Posner is hunting rabbets—the little grooves that allow you to easily remove boards.

Mentor’s John Day takes a jaunt inside Audi’s new TT Roadster, where the steering wheel isn’t round and where you can talk to your car in a natural voice. Do you think the airbag is oblong?

Cadence’s Richard Goering follows a panel discussion about virtual platforms and high-level synthesis—and the question of whether one model can serve both.

Mentor’s Scott Salzwedel notes that the FDA is clamping down on the software in medical devices. Think in terms of certifiable software.

Cadence’s Jeffrey Chung digs into training modes inside the DDR interface in a five-minute video tutorial.

And in case you missed the most recent Low Power-High Performance newsletter, here are some noteworthy blogs:

Executive Editor Ann Steffora Mutschler notes that a number of advanced techniques exist to help design engineers save power, but there is a cost involved.

Ansys-Apache’s Vic Kulkarni writes that excessive power consumption is a problem everyone needs to bring under control.

Cadence’s Brian Fuller examines the fourth major era of computing.

Synopsys’ Neill Mullinger notes that increased productivity for memory compliance testing and low power in UVM environments are essential for SoC verification.

Atrenta’s Larry Vivolo questions what’s wrong with his car and why that’s relevant to semiconductor design.

Rambus’ Frank Ferro writes that total memory bandwidth will need to increase about 33% per year to keep pace with processor improvements.

ARM’s Ian Johnson looks at how to enable the next generation of smart and connected devices.