Blog Review: Oct. 26

Designing in the cloud; specialized SystemVerilog classes; COTS chiplets; ultra-cheap smartphones.


Synopsys’ Teng-Kiat Lee and Sandeep Mehndiratta argue that IC design in the cloud can support an existing on-prem strategy, enable large and small enterprises to manage cost and capacity more effectively, and offer security for valuable semiconductor IP.

Siemens EDA’s Chris Spear finds that SystemVerilog classes are a good way to encapsulate both variables and the routines that operates on them, and presents a way to reuse the methods but change the type of properties.

Cadence’s Paul McLellan considers naming conventions for sticking multiple die in a package and key questions for whether off-the-shelf chiplets will be a viable market.

Arm’s Neil Fletcher considers the technical capabilities needed for ultra low-cost smartphones that could improve internet accessibility in emerging economies and help bridge the digital divide.

Renesas’ Graeme Clark explains the Data Operations Circuit (DOC), a microcontroller peripheral that can provide performance advantages in real time applications, allowing tasks to be offloaded from the CPU, improving the response time to asynchronous events, and potentially reducing power consumption.

Ansys’ Kerry Herbert points to eye-tracking technology as a key enabler for AR/VR that can help reduce vergence-accommodation conflict, which can lead to focusing problems, eye strain, and visual fatigue.

A Riscure writer provides a primer on electro-magnetic fault injection, which involves creating an electromagnetic field over the chip that could cause a change in the chip’s behavior and can be used to try to bypass a security mechanism or retrieve encryption keys.

A Rambus writer points to the latest updates to PCIe and CXL, which promise to increase data center performance and scalability while reducing the total cost of ownership.

In a blog for SEMI, Intel’s Garima Gautam and ASM International’s William Olson consider the methods, tools, and best practices that will advance and promote diversity across the global supply chain and  develop a comprehensive, global strategy for increasing supply chain resilience.

Plus, catch up on the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

SEMI’s Gity Samadi and NextFlex’s Paul Semenza look at novel interconnect and attach techniques from FLEX 2022 for more compact, lightweight, and higher performance flexible electronics.

Coventor’s Qingpeng Wang shows how to overcome limited wafer test data when choosing a DRAM patterning scheme.

Amkor’s Vineet Pancholi and Dennis Dinawanao present test steps and parameters for new and established power technologies.

Rambus’ Emma-Jane Crozier points to why security for accelerator blades is different, and what to do about it.

Synopsys’ Firooz Massoudi and Ash Patel look at how timing uncertainty in modern digital designs can make it difficult to determine the minimum supply voltage.

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