Blog Review: Sept. 17

Ansys’ Benoit Debbaut looks at the Pitch drop experiment, which was started in 1927 (yes, that date is correct) to observe the excruciatingly slow movement of a thick liquid weighted down by gravity. Since inception, a total of nine drops have fallen. So when will the tenth drop fall? Place your bets…when you get around to it.

Mentor’s Matthew Ballance highlights an interesting challenge for verification tests: Verification occurs in multiple environments ranging from SystemC to UVM, with some embedded software thrown in. Just adding more tests sometimes can have a negative impact.

Synopsys’ Eric Huang is back after a long hiatus, and with a vengeance—this time to challenge the risk from USB peripherals. Is anyone missing their keyboard?

Cadence’s Brian Fuller attends a discussion that seeks to solve a persistent question these days: What is IoT and what isn’t it? And perhaps more important, what technology is necessary to make it all work?

ARM’s Kris Flautner looks at the real value of the “I” in “IoT” and why it’s so important to get this piece right even if some of the end applications don’t matter.

Applied Materials’ Er-Xuan Ping attends a panel discussion that hinged on whether 3D NAND is a disruptive technology for flash storage. Guess what the panel concluded.

Ansys’ Bill Vandermark scoured the Internet to find the five engineering articles of the week. Of particular note: There is almost no garbage in Sweden. And there is a new motor being tested that relies on electric fields rather than magnetism.

Mentor’s Colin Walls digs into hypervisors on multicore chips. It seems like an obvious way to use cores asymmetrically, but it doesn’t always work that way.

Synopsys’ Mick Posner blows apart three myths about FPGA prototypes that he claims came out of the dark ages. It’s amazing what they came up with back then.

Cadence’s Richard Goering attends PCB West and observes that IPC-2581 is gaining momentum to bring design data into manufacturing as a single file.

ARM’s Jem Davies has come up with four seemingly absurd ideas. But are they really useless?

Mentor’s Nazita Saye finds that in engineering there is no such thing as a failure—only an outcome. This is where engineers and accountants draw a line in the sand.

And in case you missed last week’s Low Power-High Performance newsletter, here are some standout blogs:

Executive Editor Ann Mutschler observes that while a lot of attention is showered on power reduction for handhelds and IoT apps, concerns are much different on the other side.

Cadence’s Brian Fuller argues that we need a visionary to offer glimpses into what technology can become, not just modifications of what is already here.

ARM’s Leah Schuth digs deep into design-specific solutions to increase PPA and cut time to market.

Synopsys’ Navraj Nandra finds much already available to reduce a design’s overall power consumption.

Mentor Graphics’ Jim Kenney writes that EDA vendors need to provide designers with an option to trade off power estimation granularity with processing time during different phases of development.

Ansys-Apache’s Preeti Gupta questions whether RTL power can adequately model key physical aspects of clocks to make reliable power-related decisions, and what complexities are added after 20nm.

Calypto’s Anand Iyer digs into why it is so important to do analysis at the RTL.

Atrenta’s Kiran Vittal observes how important it is to secure manufacturing test robustness at the RTL.

Rambus’ Joe Gullo notes that the pace, cost and complexity of scaling make it impossible to proceed without partners.