Why Parallelization Is So Hard
By Brian Bailey - 30 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Not Enough Respect For SoC Interconnect
By K. Charles Janac - 30 Jul, 2018 - Comments: 0

For high-volume system-on-chip (SoC) applications—artificial intelligence (AI), automotive, mobility, solid state drives and more—effective interconnect technology can generate hundreds of millions of dollars in revenue due to smaller chip area, better functionality and faster delivery of SoC platforms. State-of-the-art interconnect technology also allows chip designers to create SoC deriva... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Jul, 2018 - Comments: 0

Trade issues China and the United States are embroiled in a trade war. What is the impact? In testimony submitted to the Office of the United States Trade Representative (USTR) on the proposed tariffs on Chinese products, Consumer Technology Association (CTA) Vice President of International Trade Sage Chandler argues tariffs negatively impact businesses and consumers as well as fail to corr... » read more

Pros, Cons Of ML-Specific Chips
By Ed Sperling - 27 Jul, 2018 - Comments: 1

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. To view part one, click here. Part two is here. SE: Is the industry's knowledge of machine learning keeping up with th... » read more

Will FPGAs Work As Expected?
By Ed Sperling - 27 Jul, 2018 - Comments: 1

OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs. https://youtu.be/RFlP2Z_-Yqs » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Jul, 2018 - Comments: 0

Tools & IP Cadence uncorked the latest version of the Sigrity signal integrity analysis family of tools, adding a 3D design and 3D analysis environment integrated with Allegro PCB tools that allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB for modeling and optimization as one structure. It also adds full Rigid-Flex PCB extraction from... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 27 Jul, 2018 - Comments: 1

Automotive Tech Marvell Technology Group opened its automotive electromagnetic compatibility lab in North America. The facility is CISPR 25-qualified and gives the chip company the capability to conduct in-house electrostatic discharge, emission, and immunity testing. Marvell also reported that its 88Q2112 offering received a mark of 100% in conformance testing outlined by the Japan Automotive... » read more

Solving Systemic Complexity
By Ed Sperling - 26 Jul, 2018 - Comments: 0

EDA and IP companies have begun branching out in entirely new directions over the past 12 to 18 months, pouring resources into entirely different problems than electrostatic issues and routing complexity. While they're still focused on solving complexity at 10/7/5nm, they also recognize that enabling Moore's Law isn't the only opportunity. For an increasing number of new and established chip... » read more

A New Era For EDA
By Brian Bailey - 26 Jul, 2018 - Comments: 0

For almost the entirety of my time in EDA, which is approaching 40 years, the total number of design starts has been declining. A lot of this is to be expected. Semiconductors was the new and exciting world where startups popped up hoping to make it big in Silicon Valley, or indeed to become the next Silicon Valley, Forest, Swamp or Desert. Many of them didn't manage to get beyond a neat concep... » read more

Functional Safety: Art Or Science?
By Sergio Marchese - 26 Jul, 2018 - Comments: 0

Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our increasingly connected world, where billions of IoT devi... » read more

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