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Week In Review: Design, Low Power

Interconnect modeling; 56G Ethernet PHY; FPGA timing in the cloud; EDA, IP sales up.

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Tools & IP
Cadence uncorked the latest version of the Sigrity signal integrity analysis family of tools, adding a 3D design and 3D analysis environment integrated with Allegro PCB tools that allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB for modeling and optimization as one structure. It also adds full Rigid-Flex PCB extraction from a single layout database and faster IC package modeling.

Synopsys debuted 56G Ethernet PHY IP targeting 400Gbps hyperscale data center SoCs. The PHY supports single and aggregated link rates from 10G to 400G Ethernet while meeting the PAM-4 and NRZ signaling. The receiver features a multi-loop clock and data recovery circuit for better jitter performance, as well as a full-featured DSP.

Cadence also updated its Voltus IC Power Integrity Solution with an extensively parallel algorithm option employing distributed processing technology for power grid signoff at advanced nodes According to the company, the new algorithm provides performance improvements up to 5X and works on giga-scale designs. It has been used by HiSilicon to sign off mobile and HPC production designs.

Plunify launched its FPGA timing and analytics tool, InTime, on the Plunify Cloud platform for on-demand development, optimization, testing and deployment of Xilinx FPGAs using the Vivado Design Suite. The Plunify Cloud plugin for Vivado allows users to offload compute-intensive builds to the cloud or directly access a preloaded cloud machine.

Dolphin Integration released a new free version of its IDE supporting RISC-V microcontrollers. The new release includes support for more RISC-V ISA extensions as well as a stack-unwinding tool in the debug toolbox and new pre-defined MCU subsystems for the company’s RV32 Tornado SoC.

Deals
C-SKY Microsystems, part of Alibaba, licensed UltraSoC’s embedded analytics technology for use in SoCs targeting AI-based applications. The companies plan a long-term partnership.

A team from Cadence, Carnegie Mellon University, and Nvidia will be part of DARPA’s Intelligent Design of Electronic Assets (IDEA) program aimed at creating an automated, unified layout generator for mixed-signal integrated circuits, systems-in-package, and printed circuit boards.

Numbers
EDA and IP revenues reached $2.309 billion in the first quarter of 2018, up 7.8% from Q1 2017, according to the ESD Alliance’s Market Statistics Service. The four-quarters moving average rose 9.1%. Every product category and region showed positive growth, with double digit increases for both IC Physical Design & Verification (19.3%) and PCB & MCM (13.8%). Hiring remains strong, with tracked companies reporting 41,110 employees, up 10.4% from the same time last year and 2.9% from the previous quarter.

Cadence reported second quarter 2018 financial results with revenue of $518 million. On a GAAP basis, net income was $0.27 per share, while non-GAAP income was $0.45 per share. The company recently adopted new reporting standards; under the prior system, income for the quarter was $515 million, up 7.5%. GAAP earnings were $0.26 per share, up 4%, and non-GAAP earnings were $0.44 per share, up 29.4%. “Multiple technology waves, especially machine learning, are driving increased design activity,” noted Cadence CEO Lip-Bu Tan.



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