Power-Aware Static Checks: Static Checker Results And Debugging Techniques
By Progyna Khondkar - 17 Jul, 2018 - Comments: 0

In Part 1 of this three article series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we discussed the features of the static verification library and described best static verification practices. Part 3 concludes this series with details of static PA verification tool procedures using a real example to analyze PA-Stati... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Explaining Adaptive Voltage Scaling And Dynamic Voltage Frequency Scaling
By Ramsay Allen - 17 Jul, 2018 - Comments: 0

A Q&A with Moortec CTO Oliver King. What exactly do we mean by Adaptive Voltage Scaling versus Dynamic Voltage Frequency Scaling? Adaptive Voltage Scaling (AVS) involves the reduction of power by changing the operating conditions within an ASIC in a closed loop. Dynamic Voltage Frequency Scaling (DVFS), on the other hand, is a power management technique where the voltage is increased ... » read more

Architecting For AI
By Ann Mutschler - 17 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about what is needed today to enable artificial intelligence training and inferencing with Manoj Roge, vice president, strategic planning at Achronix; Ty Garibay, CTO at Arteris IP; Chris Rowen, CEO of Babblelabs; David White, distinguished engineer at Cadence; Cheng Wang, senior VP engineering at Flex Logix; and Raik Brinkmann, president and CEO of O... » read more

Enabling Integrated ADAS Domain Controllers With Automotive IP
By Ron DiGiuseppe - 17 Jul, 2018 - Comments: 0

Traditionally, the electronic control units (ECUs) for individual Advanced Driver Assistance System (ADAS) applications have been placed throughout the car. The latest automotive architecture will integrate ECUs for multiple ADAS applications into centralized domains to combine multiple ADAS functions. The new class of integrated domain controller ECUs utilize data transferred from the car’s ... » read more

Five DAC Keynotes
By Brian Bailey - 17 Jul, 2018 - Comments: 0

The ending of Moore's Law may be about to create a new golden age for design, especially one fueled by artificial intelligence and machine learning. But design will become task-, application- and domain-specific, and will require that we think about the lifecycle of the products in a different way. In the future, we also will have to design for augmentation of experience, not just automation... » read more

Five Features Of The ‘Always-On’ Mobile Experience
By Jakub Lamik - 17 Jul, 2018 - Comments: 0

Today’s technology consumers – labeled as the ‘always on, always connected’ generation – are some of the most demanding when it comes to what they expect from their devices for work and play. Not only do consumers want devices that are able to manage their multiple demands on the go – from mobile gaming to video streaming – but they also want devices to work continuously without t... » read more

In-Design Power Rail Analysis
By Ed Sperling - 17 Jul, 2018 - Comments: 0

Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

Low Power Coverage
By Mentor, a Siemens Business - 16 Jul, 2018 - Comments: 0

Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

Fostering Thermal Design Innovation Using Chip-Package-System Analysis Techniques
By Ansys - 16 Jul, 2018 - Comments: 0

As devices continue to become smaller and more portable Moore’s Law continues to increase the number of transistors that fit within a chip albeit many predict an end to this in the near future. However new interconnect technologies that use Through-Silicon-Vias (TSVs) can place ICs next to each other using 2.5D Interposers or stack chips in 3D resulting in even greater system scaling. This co... » read more

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