The LP R&D Ecosystem
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

I don’t know about you, but I’m always fascinated to learn new things about chip design. New techniques for power reduction, new ways to use existing tools, new tools in general. Some of this is happening at universities, some in happening in industry consortiums or partnerships, and despite what some people say from time to time, there is still innovation happening within the EDA companie... » read more

How Long Will Your Battery Last?
By Ed Sperling - 12 Feb, 2015 - Comments: 0

Designing an IP block or memory subsystem to fit within a power budget is essential for building energy efficiency into hardware and software. There's only one catch—it's meaningless to the end customer. Twenty years ago this was a pretty straightforward formula. If you used a device consistently, whether it was a computer or a calculator or an electric motor, then you would burn up X numb... » read more

Who Pays For EDA Shift Left?
By Brian Bailey - 12 Feb, 2015 - Comments: 0

While working on the predictions articles for 2015 (markets, design, semiconductors, tools and flows), a number of companies talked about the great shift left that is happening in the industry. What was surprising was the number of companies that mentioned it, and in very different ways. It is clear that shift left does not mean the same thing to all people. While they all see it addressing ... » read more

The Art Of LP Analog
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

The best way to reduce power in analog chips is to make architectural changes or adopt a new architecture for the individual block. However, there are also some design techniques used to reduce power in analog circuitry. Unlike digital circuitry, which allows an engineer to leverage a low power library and optimize through a constraints file with the EDA software to reduce power, the same do... » read more

Emulation Uses Increase
By Ed Sperling - 12 Feb, 2015 - Comments: 0

For more than two decades, [getkc id="30" comment="emulation"] was a technology in search of a market. While on paper it has always made sense to speed up simulation, using hardware acceleration was so pricey that few companies could justify the cost. Fast-forward to today and emulation is a major contributor to the bottom line at all of the Big Three [getkc id="7" kc_name="EDA"] companies. ... » read more

With Responsibility Comes Power
By Brian Bailey - 12 Feb, 2015 - Comments: 0

The debate continues as to whether [getkc id="106" kc_name="power"] has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is ... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Calibrating Electronics Thermal Simulation Models
By Robin Bornoff - 12 Feb, 2015 - Comments: 0

‘Rubbish In, Rubbish Out’ is a common and well-accepted fact in the world of thermal simulation—actually any type of simulation, for that matter. Regardless of the technical capabilities of your thermal simulation tool, the accuracy of prediction will always be tightly coupled to the accuracy of the input data. In terms of electronics thermal simulation, the prediction of the internal ... » read more

Postcards From The Edge (Of The Cloud)
By Brian Fuller - 12 Feb, 2015 - Comments: 0

The view from the edge of the cloud is pretty spectacular. Out here, there’s endless possibility. But out here on the edge, there’s turbulence, the cold buffeting swirl of today’s engineering challenges. On the edge, some see the Internet of Things (IoT) stalled. I wrote about this last month. The first wave of IoT devices — especially wearables — has quickly commoditized, driven b... » read more

Low Power Trends Toward FinFET
By Mary Ann White - 12 Feb, 2015 - Comments: 0

My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

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