Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?


By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

Automating Antenna Placement Workflow With PyAEDT


Antenna designs can reach daunting levels of complexity, and nowhere is that truer than in advanced 5G and 6G systems. One of the most difficult problems in this design space is signal degradation stemming from electromagnetic (EM) interaction between the phased array antenna and the host structure itself, such as a base station or satellites. It is a pernicious issue that takes several advance... » read more

Understand The Physics Of Re-Entry Vehicles Using Numerical Modeling And Simulation


In the early years of space exploration, scientists and engineers dreamed of sending vehicles to Mars that could land on the planet's surface and explore its terrain. However, one of their biggest challenges was safely reentering the Martian atmosphere. Many early attempts at Mars missions failed because the vehicles either burned up during re-entry or crashed onto the surface. However, as tech... » read more

Leveraging Vehicle-To-Everything Sidelink Communication For Relative Localization Of Connected Automated Vehicles 


A technical paper titled “V2X Sidelink Localization of Connected Automated Vehicles” was published by researchers at CNR-IEIIT and WiLabCNIT (Italy). Abstract: "Future automated driving relies on two pillars, (i) ultra-low-latency and reliable communications, and (ii) accurate positioning information. In particular, the knowledge of vehicle positions is becoming fundamental with the incre... » read more

A Framework To Detect Capacitance-Based Analog Hardware Trojans And Mitigate The Effects


A technical paper titled “DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans” was published by researchers at Tennessee Tech University and Technische Universitat Wien. Abstract: "The global semiconductor supply chain involves design and fabrication at various locations, which leads to multiple security vulnerabilities, e.g., Hardware Trojan (HT) insertion. Although most... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs


A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

CMOS Compatible Materials With Quantum Defects Suitable For Room Temperature Applications


A technical paper titled “Thin Film Materials for Room Temperature Quantum Applications” was published by researchers at Marquette University. Abstract: "Thin films with quantum defects are emerging as a potential platform for quantum applications. Quantum defects in some thin films arise due to structural imperfections, such as vacancies or impurities. These defects generate localized el... » read more

Fabless Approach To Embed Active Nanophotonics in Bulk CMOS By Co-Designing The BEOL Layers For Optical Functionality (MIT)


A technical paper titled “Metal-Optic Nanophotonic Modulators in Standard CMOS Technology” was published by researchers at Massachusetts Institute of Technology. Abstract: "Integrating nanophotonics with electronics promises revolutionary applications ranging from light detection and ranging (LiDAR) to holographic displays. Although semiconductor manufacturing of nanophotonics in Silicon ... » read more

Applying Machine Learning to EDA, FPGA Design Automation Tools


A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. Abstract: "With the recent advances in hardware technologies like advanced CPUs and GPUs and the large availability of open-source libraries, machine learning has penetrated various domains, including Electronics Design Automation (EDA). E... » read more

The Value Of Field Solvers In Semiconductor Development Helps Drive Infineon Innovation


Parasitic extraction (PEX) helps ensure accurate circuit performance in the design and verification flow. Development of accurate PEX runsets depends on accurate and precise extraction results obtained using a full-featured field solver. Infineon selected the Calibre xACT 3D tool as their reference field solver tool of choice in the development of their next-generation semiconductor power produ... » read more

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