EDA’s Top Execs Map Out An AI-Driven Future
By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Machine Intelligence on Wireless Edge Networks with RF Analog Architecture (MIT, Duke)
By Technical Paper Link - 21 Jun, 2025 - Comments: 0

A new technical paper titled "Machine Intelligence on Wireless Edge Networks" was published by researchers at MIT and Duke University. Abstract "Deep neural network (DNN) inference on power-constrained edge devices is bottlenecked by costly weight storage and data movement. We introduce MIWEN, a radio-frequency (RF) analog architecture that "disaggregates" memory by streaming weights wirele... » read more

Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing (Infineon, U. Padova et al.)
By Technical Paper Link - 21 Jun, 2025 - Comments: 0

A new technical paper titled "Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing" was published by researchers at Infineon Technologies, University of Padova and University of Bologna. Abstract "In the semiconductor sector, due to high demand but also strong and increasing competition, time to market and quality are key factors in securing significant marke... » read more

Chip Industry Week in Review
By The SE Staff - 20 Jun, 2025 - Comments: 0

Texas Instruments will invest more than $60 billion to build and expand seven semiconductor fabs in Texas and Utah, supporting more than 60,000 U.S. jobs. Chinese automakers — including SAIC Motor, Changan, Great Wall Motor, BYD, Li Auto and Geely — are aiming to launch new models with 100% homemade chips, some as early as 2026, reports Nikkei Asia. Marvell introduced 2nm custom SRAM ... » read more

Examining Mechanical Deformation In Advanced Logic Devices To Enhance Yield
By Sandy Wen - 19 Jun, 2025 - Comments: 0

By Sandy Wen and Jacky Huang As dimensions shrink and aspect ratios increase in advanced logic devices, it is increasingly important to reduce structural device variation. Structural device variations can be a proxy for device yield. These variations might include critical dimension (CD), gate CD, gate height, and proximity between neighboring vias. One contributor to structural device v... » read more

Power Delivery Challenges For AI Chips
By Gregory Haley - 19 Jun, 2025 - Comments: 0

As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

How To Catch “Disappearing” Latent Defects
By Mike LaTorraca - 19 Jun, 2025 - Comments: 0

Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

Variable Bias Completes The PLDC Model And Offers Superior MPC Results
By Aki Fujimura - 19 Jun, 2025 - Comments: 0

This is the third in a three-blog series on PLDC. The first installment was “Improving Uniformity and Linearity for All Masks,” from January 29, 2025. The second blog was “Three Ways Curvy ILT Together with PLDC Improves Wafer Uniformity,” from April 18, 2025. In 2024, the eBeam Initiative Luminaries Survey found that the number one concern in adoption of curvilinear mask features wa... » read more

Improving Fab Engineering Efficiency With Autonomous Data Analytics
By Peter Barar - 19 Jun, 2025 - Comments: 0

During my earlier career as a process integration engineer, one of my primary responsibilities was to find yield enhancement opportunities by investigating underlying relationships between bin failures and process parameters within the fab. While performing this analysis, there were many impediments to identifying relationships among different data types: sort maps, electrical test maps, parame... » read more

Physics Limits Interposer Line Lengths
By Bryon Moyer - 19 Jun, 2025 - Comments: 0

Electrical interposers provide a convenient surface for mounting multiple chips within a single package, but even though interposer lines theoretically can be routed anywhere, insertion losses limit their practical length. Lines on interposers — and on silicon interposers in particular — can be exceedingly narrow. Having a small cross-section makes such lines resistive, degrading signals... » read more

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