V-NAND PUFs (Seoul National University, SK hynix)


A new technical paper titled "Concealable physical unclonable functions using vertical NAND flash memory" was published by researchers at Seoul National University and SK hynix. The paper proposes "a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase." Find the technical paper here. June 2025. Park, SH., Koo, RH., Yang,... » read more

Quantifying The PFAS Impact In ICs Manufacturing (Harvard University)


A new technical paper titled "Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems" was published by researchers at Harvard University and Mohamed Bin Zayed University of AI (MBZUAI). "The electronics and semiconductor industry is a prominent consumer of per- and poly-fluoroalkyl substances (PFAS), also known a... » read more

Customizing An LLM Tailored Specifically For VHDL Code And Design Of High Performance Processors (IBM)


A new technical paper titled "Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors" was published by researchers at IBM. Abstract "The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the ... » read more

Arithmetic Intensity In Decoding: A Hardware-Efficient Perspective (Princeton University)


A new technical paper titled "Hardware-Efficient Attention for Fast Decoding" was published by researchers at Princeton University. Abstract "LLM decoding is bottlenecked for large batches and long contexts by loading the key-value (KV) cache from high-bandwidth memory, which inflates per-token latency, while the sequential nature of decoding limits parallelism. We analyze the interplay amo... » read more

Mastering Chiplet Design


The semiconductor industry is undergoing a fundamental shift from monolithic chip designs to chiplet-based architectures. This modular approach promises enhanced performance, cost efficiency, and scalability, but it also brings unique system-level verification challenges that design teams must overcome. Chiplet systems break different functions into smaller, separate dies, improving yield an... » read more

Chip Industry Technical Paper Roundup: June 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=436 /] Find more semiconductor research papers here. » read more

Research Bits: June 3


Imaging power electronics Researchers from the Institute of Science Tokyo, Harvard University, and Hitachi used diamond quantum sensors to analyze the magnetization response of soft magnetic materials used in power electronics. The method can simultaneously image both the amplitude and phase of AC stray fields over a wide frequency range up to 2.3 MHz. It uses a diamond quantum sensor with ... » read more

On The Ground At ECTC 2025


Senior Executive Editor Laura Peters examines the the hot topics at last week's IEEE's Electronic Components and Technology Conference, including the impact of hardware-software integration on power consumption, co-packaged optics, hybrid bonding, and fan-out panel-level packaging. https://youtu.be/yBDKqrPQBl4   » read more

Photomask Japan 2025: A Strong Signal For The Future Of Our Industry


Photomask Japan (PMJ) 2025 was, without a doubt, the most exciting edition I’ve attended in recent years. From a surge in attendance to a packed agenda full of technical depth and forward-looking insights, this year’s event reflected the growing momentum and innovation across the photomask and eBeam ecosystem. Let’s start with the numbers—624 attendees. That’s a significant jump fr... » read more

Accelerating Scalable Computing


By Shivi Arora and Sue Hung Fung As computing demands for HPC, AI/ML, and cloud infrastructure grow, modular architectures are replacing traditional monolithic System-on-Chip (SoC) designs. These legacy designs are increasingly expensive and difficult to scale due to ever-increasing silicon complexity. In response, the industry is embracing chiplet-based System-in-Package (SiP) solutions,... » read more

← Older posts Newer posts →