Using Deep Learning ADC For Defect Classification For Automatic Defect Inspection


In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of... » read more

The Crucial Role Of High-Performance Computing In 2024: Balancing Cost And Innovation


We live in a world where digital queries run the Information Superhighway and in turn, our lives. This means that the importance of High-Performance Computing (HPC) cannot be overstated. The technology behind this continues to be a cornerstone for advancing our world and improving productivity. To put it another way, can you imagine a day, a week, when you are not querying something? So, let... » read more

Improvement of High-Gradation DDIC Device Test Yield By T6391 High-Accuracy Measurement Solution


For DDIC (Display Driver IC) for OLED (Organic Light Emitting Diode) displays for smartphones and IT displays (tablets, laptops) and head mounted displays for AR (Augmented Reality)/VR (Virtual Reality), the output voltage will be divided into more highly-defined steps than in the past. A new per-pin digitizer and comparator module “LCD HP” was developed to measure the output voltage of the... » read more

Return On Investment Of A Pre-Reflow AOI System


This paper describes the losses from defects at the placement process in the SMT line. Two case studies of European and Taiwanese SMT manufacturers illustrate the actual losses from their defects. An evaluation method to select a pre-reflow AOI system maximizing the return on investment (ROI) is introduced. In the end, ROIs of three commercial pre-reflow AOI systems are compared to demonstrate ... » read more

Doing More At Functional Test


Experts at the Table: Semiconductor Engineering sat down to discuss the increasing importance of functional test, especially in high-performance computing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center products); Nitza Basoco, tec... » read more

Research Bits: May 13


On-chip microcapacitors Scientists from Lawrence Berkeley National Laboratory and University of California Berkeley developed microcapacitors with ultrahigh energy and power density that could be used for on-chip energy storage. The microcapacitors were made with thin films of hafnium oxide (HfO2) and zirconium oxide (ZrO2) engineered to achieve a negative capacitance effect, which increase... » read more

Reset Domain Crossing Verification


By Reetika and Sulabh Kumar Khare To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and hardware functional safety as they can be asserted to speedily recover the system onboard to an initial state and clear any pending errors or events. By definiti... » read more

Chip Industry Technical Paper Roundup: May 13


New technical papers added to Semiconductor Engineering’s library this week. [table id=225 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


Synopsys refocused its security priorities around chips, striking a deal to sell off its Software Integrity Group subsidiary to private equity firms Clearlake Capital Group and Francisco Partners for about $2.1 billion. That deal comes on the heels of Synopsys' recent acquisition of Intrinsic ID, which develops physical unclonable function IP. Sassine Ghazi, Synopsys' president and CEO, said in... » read more

SRAM Security Concerns Grow


SRAM security concerns are intensifying as a combination of new and existing techniques allow hackers to tap into data for longer periods of time after a device is powered down. This is particularly alarming as the leading edge of design shifts from planar SoCs to heterogeneous systems in package, such as those used in AI or edge processing, where chiplets frequently have their own memory hi... » read more

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