Toward Agentic Verification


Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

Observability Is Essential For Modern Silicon


Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Why Your NoC Verification Strategy Must Consider Using Formal


By Ashish Darbari and Bing Xue It’d be inconceivable these days to design a modern high-performance SoC without a network-on-chip (NoC) fabric. AI hyperscalers are inherently multi-threaded and rely on using hundreds of processing elements (PEs). Crossbar-based fabric would just not scale. What also changes with the adoption of the NoC is how to handle coherency between PEs. ACE is no long... » read more

Automating Traditional PCB Layout Verification With Electrically Based Design Rule Checks


Electrical verification and sign-off of a printed circuit board (PCB) is a challenging, tedious, and manual process. If time permits, this visual inspection to catch errors that might cause costly respins is done throughout the PCB layout process, but traditionally it is performed only once at the end of the design cycle. This approach creates significant project delays when issues are discover... » read more

Using SystemC TLM Modeling To Solve AI Data Movement Challenges


In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, and accelerator density. But engineers building these systems understand the harder truth. Compute performance matters only when data arrives at the right rate, with the right latency, and without ... » read more

Foundation Model For Physics: The Next Layer Of Intelligence For Engineering


Over the past decade or so, foundation models have emerged as the dominant paradigm for interacting with language, images, and code. Large Language Models (LLMs) can generate text. Vision models can interpret images. Multimodal systems can connect the two seamlessly. But one domain has not yet seen the same foundation-model-level shift: validated, deterministic reasoning over the physical wo... » read more

Faster Verification Debug With AI


Every stage of semiconductor development takes longer and requires more effort with each new generation of chips. At no stage is this more apparent than functional verification. Industry consensus is that verification consumes roughly two-thirds of development time and resources. Within verification, debug is the most challenging step, consuming a third to two-thirds of the effort. Any serious ... » read more

Wafer-Scale vs. Chiplets: The New War? Part 1


Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has effectively acknowledged: incremental chip scaling can no longer keep pace with what AI infrastructure demands. Radical approaches are earning serious consideration and serious capital. Cerebras... » read more

The Shape Of Prompts: Exploring Their Effect On Inference Infrastructure


AI inference prompts exhibit a shape-shifting behavior, arriving in many forms and attempting to fit themselves within the constraints of the inference stack. Ultimately, it is the design of the inference infrastructure that determines whether it can sustain a large volume of prompts or only a limited number. Prompts are not uniform transactions; they represent dynamic workload profiles whose ... » read more

A Bench-To-In-Field Telemetry Platform For Data Center Power Management


By Aakash Jani and Venkatesh Santhanagopalan NVIDIA's Blackwell platform delivered roughly 15% lower energy and 13% higher throughput [1]. Those gains came from hardware-firmware co-design that matches operating points to each workload, not a new process node. Most SoCs do not adapt: their margins are set and frozen the day silicon ships, based on the workloads measured at the bench. The mi... » read more

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