A Scalable Answer To Advanced-Node Characterization


If you're working on standard-cell libraries at 28 nm or below, you already know the math isn't in your favor. At the 130 nm node, a typical library had fewer than 100 cells and a handful of PVT corners. Fast-forward to 16/14 nm and beyond, libraries now contain 1,200+ cells across 200+ PVT corners. Every new SoC tape-out demands broader coverage for design robustness, and the characte... » read more

Overcoming Bottlenecks In Data Movement


AI is all about data. There is more data to process, store, and move, and more tradeoffs required to do that efficiently and with enough flexibility to handle changes in future workloads. Nandan Nayampally, chief commercial officer at Baya Systems, talks about networks on chip and networks across chip, what the choke points are for data movement, and where and when data coherency makes sense. » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology


Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table:... » read more

Deterministic, Solver-Accurate Thermal and Warpage Analysis at Manufacturing Resolution for Advanced 2.5D HBM Packages


Thermal management has become the defining bottleneck in high-performance computing (HPC) and AI accelerator packaging. Modern packages integrate high-power ASICs with multiple High Bandwidth Memory (HBM) stacks on a silicon interposer, creating tightly coupled thermal and mechanical interactions. Die-to-die thermal crosstalk elevates HBM junction temperatures, while coefficient of thermal e... » read more

Rethinking AI-Scale Data Center Validation


The rapid growth of AI workloads is transforming AI data center networking, exposing critical limitations in traditional Ethernet validation and network testing methodologies. As data centers adopt 1.6T Ethernet, 224G SerDes and optical lanes, and tightly coupled GPU fabrics, networks must deliver ultra-high bandwidth, low latency, and predictable performance under dynamic east-west traffic con... » read more

Blog Review: May 27


Cadence's Igor Krause explains Precision Time Measurement (PTM), a PCIe feature that enables precise coordination of events across multiple components with independent local time clocks. Siemens' John McMillan suggests the way to achieve trusted traceability across the semiconductor supply chain is by implementing a blockchain-based distributed ledger paired with a secure digital twin. Sy... » read more

Multiphysics Fusion Technology for Multi-Die Designs Explained


Multiphysics issues are no longer a late-stage problem. Multi-die designs introduce tightly coupled electrical, thermal, electromagnetic, and electromechanical challenges that impact performance and reliability. This eBook shows why multiphysics analysis must move earlier in the design flow, and how a unified approach enables continuous validation from exploration through signoff. What You�... » read more

Characterization of GPU-based Inference for Reasoning-Centric LLMs (Micron, Argonne)


Researchers from Micron Technology and Argonne National Laboratory have released “Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles”. Abstract “The transition from standard generative AI to reasoning-centric architectures, exemplified by models capable of extensive Chain-of-Thought (CoT) processing, marks a fundamental paradigm shift i... » read more

Chip Industry Technical Paper Roundup: May 26


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving 🔗 Nvidia, Groq Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning 🔗 USC, University of Wisconsin-Madison Water-based, large-scale transfer of... » read more

Research Bits: May 26


Simultaneous energy generation and emission Researchers from the Institute of Science Tokyo and University of Osaka designed an organic semiconductor device that can both generate electricity from light and emit bright visible light. The researchers used two multiple-resonance thermally activated delayed fluorescence (MR-TADF) molecules, v-DABNA and QAO, in a simple layered structure. Their... » read more

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