Detecting Defect-Induced Silent Data Corruptions in CPUs (Stanford, Google)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Stanford University and Google have published “ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions”. Abstract “Hyperscaler reports of silent data corruptions (SDCs)—presumed to be caused by silicon manufacturing defects—have motivated the development of functional tests for detecting defective CPUs and their use in h... » read more

Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung)
By Technical Paper Link - 25 May, 2026 - Comments: 0

A new technical paper, "Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory," was published by researchers from University of Seoul and Samsung Electronics. Abstract "This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggres... » read more

An Agent-Driven End-to-End HW-SW Co-Design Benchmark for Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Columbia University and IBM Research have released “HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip”. Abstract “Large language models (LLMs) are adopted for software and hardware design, yet these domains are still evaluated separately. Software benchmarks typically assume fixed hardware targets, while hardware be... » read more

Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Grenoble INP - UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, a... » read more

Improving GPU Energy Efficiency With Component-Level Power Management (AMD)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from AMD released “CompPow: A Case for Component-level GPU Power Management”. Abstract “The ever increasing demand for ML-driven intelligence in a wide spectrum of domains has led to ubiquity of GPUs. At the same time, GPUs are notorious for their power consumption needs and often dominate power allocation in a typical ML datacenter. While datacenter-level power opti... » read more

Chip Industry Week In Review
By The SE Staff - 22 May, 2026 - Comments: 0

Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Large-scale, SRAM-based LLM Inference Deployment (Groq)
By Technical Paper Link - 21 May, 2026 - Comments: 0

A new technical paper, "SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving," was published by researchers at Nvidia, with work done while at Groq. Abstract "The proliferation of large language models (LLMs) demands inference systems with both low latency and high efficiency at scale. GPU-based serving relies on HBM for model weights and KV caches, creating a memory bandwidth b... » read more

Beyond Ideal Crystals: The Case For Scale In Atomistic Modeling
By Anders Blom - 21 May, 2026 - Comments: 0

Almost all computer simulations face the same trade-off: larger models can be more realistic and therefore more useful, but they also take longer to run. Engineers and scientists are therefore faced with an almost daily challenge of choosing a model that is detailed enough to capture the important details without making the calculation impractically expensive. "All models are wrong, but some... » read more

Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill
By HJ Kim - 21 May, 2026 - Comments: 0

As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch mo... » read more

With Chiplets, What Role Does Economics Play?
By Bryon Moyer - 21 May, 2026 - Comments: 1

Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

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