Next-Gen High-Speed Communication In Data Centers
By Ed Sperling - 21 Aug, 2024 - Comments: 0

Data centers are being flooded with data. While more of it needs to be processed locally, much of it also needs to be moved around within a system and between systems. This has put a spotlight on a variety of new optical technologies and methodologies. Yang Zhang, senior product marketing manager at Cadence, talks about the rapid increase in different types of optics and optical scenarios being... » read more

Blog Review: Aug. 21
By Jesse Allen - 21 Aug, 2024 - Comments: 0

Cadence's Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions. Siemens' John McMillan introduces an advanced packaging flow for Intel's Embedded ... » read more

3.5D: The Great Compromise
By Ed Sperling - 21 Aug, 2024 - Comments: 1

The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Chip Industry Technical Paper Roundup: August 20
By Linda Christensen - 20 Aug, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=252 /] More ReadingTechnical Paper Library home » read more

Research Bits: Aug. 20
By Jesse Allen - 20 Aug, 2024 - Comments: 0

EUV mirror interference lithography Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly. Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two id... » read more

A Generic Approach For Fuzzing Arbitrary Hypervisors
By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “HYPERPILL: Fuzzing for Hypervisor-bugs by Leveraging the Hardware Virtualization Interface” was presented at the August 2024 USENIX Security Symposium by researchers at EPFL, Boston University, and Zhejiang University. Abstract: "The security guarantees of cloud computing depend on the isolation guarantees of the underlying hypervisors. Prior works have presented... » read more

A Novel Attack For Depleting DNN Model Inference With Runtime Code Fault Injections
By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “Yes, One-Bit-Flip Matters! Universal DNN Model Inference Depletion with Runtime Code Fault Injection” was presented at the August 2024 USENIX Security Symposium by researchers at Peng Cheng Laboratory, Shanghai Jiao Tong University, CSIRO's Data61, University of Western Australia, and University of Waterloo. Abstract: "We propose, FrameFlip, a novel attack ... » read more

Uncovering A Significant Residual Attack Surface For Cross-Privilege Spectre-V2 Attacks
By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “InSpectre Gadget: Inspecting the Residual Attack Surface of Cross-privilege Spectre v2” was presented at the August 2024 USENIX Security Symposium by researchers at Vrije Universiteit Amsterdam. Abstract: "Spectre v2 is one of the most severe transient execution vulnerabilities, as it allows an unprivileged attacker to lure a privileged (e.g., kernel) victim into... » read more

Data Memory-Dependent Prefetchers Pose SW Security Threat By Breaking Cryptographic Implementations
By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “GoFetch: Breaking Constant-Time Cryptographic Implementations Using Data Memory-Dependent Prefetchers” was presented at the August 2024 USENIX Security Symposium by researchers at University of Illinois Urbana-Champaign, University of Texas at Austin, Georgia Institute of Technology, University of California Berkeley, University of Washington, and Carnegie Mellon U... » read more

A New Low-Cost HW-Counterbased RowHammer Mitigation Technique
By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation” was presented at the August 2024 USENIX Security Symposium by researchers at ETH Zurich. Abstract: "We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening Ro... » read more

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