Power/Performance Bits: Nov. 16
By Jesse Allen - 16 Nov, 2021 - Comments: 0

Light-emitting memory Researchers from Kyushu University and National Taiwan Normal University propose a 'light-emitting memory' based on a perovskite that can simultaneously store and visually transmit data. The team used the idea in conjunction with resistive RAM (RRAM), in which states of high and low resistance represent ones and zeros. "The electrical measurements needed to check the r... » read more

An FPGA-Based ECU for Remote Reconfiguration in Automotive Systems
By Technical Paper Link - 15 Nov, 2021 - Comments: 0

Abstract: "Growing interest in intelligent vehicles is leading automotive systems to include numerous electronic control units (ECUs) inside. As a result, efficient implementation and management of automotive systems is gaining importance. Flexible updating and reconfiguration of ECUs is one appropriate strategy for these goals. Software updates to the ECUs are expected to improve performance ... » read more

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications
By Technical Paper Link - 15 Nov, 2021 - Comments: 0

Abstract: "The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row Refresh (TRR). At a high level, TRR detects and refreshes potential RowHammer-victim rows, but its exact are not openly disclose... » read more

AI/ML Workloads Need Extra Security
By Bryon Moyer - 15 Nov, 2021 - Comments: 0

The need for security is pervading all electronic systems. But given the growth in data-center machine-learning computing, which deals with extremely valuable data, some companies are paying particular attention to handling that data securely. All of the usual data-center security solutions must be brought to bear, but extra effort is needed to ensure that models and data sets are protected ... » read more

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract: "Characterization of real DRAM devices has enabled findings in DRAM device properties, which has led to proposals that significantly improve overall system performance by reducing DRAM access latency and power consumption. In addition to improving system performance, a deeper understanding of DRAM technology via characterization can also improve device reliability and security. The... » read more

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
By Technical Paper Link - 14 Nov, 2021 - Comments: 0

Abstract "RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability worsens as DRAM cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern DRAM chips, including chips previously marketed as RowHammer-safe, are even more vulnerable to RowHammer than... » read more

Making BaZrS3 Chalcogenide Perovskite Thin Films by Molecular Beam Epitaxy
By Technical Paper Link - 13 Nov, 2021 - Comments: 0

Abstract: We demonstrate the making of BaZrS3 thin films by molecular beam epitaxy (MBE). BaZrS3 forms in the orthorhombic distorted-perovskite structure with corner-sharing ZrS6 octahedra. The single-step MBE process results in films smooth on the atomic scale, with near-perfect BaZrS3 stoichiometry and an atomically-sharp interface with the LaAlO3 substrate. The films grow epitaxially via tw... » read more

AKER: A Design and Verification Framework for Safe and Secure SoC Access Control
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. In security-critical applications, IP cores have different privilege levels for accessing shared resources, which must be regulated by an access control system. AKER is a design and verification framework for SoC access control. AKER builds ... » read more

Dynamic in-chip current distribution simulation technology for power device layout design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Chip Package Co-design and Physical Verification for Heterogeneous Integration
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven... » read more

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