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Chip Package Co-design and Physical Verification for Heterogeneous Integration

Integration and verification methodology with a physical design driven approach which is data-light and can be adapted anytime in the design process. It’s applicable to any heterogeneous integration technology involving multiple dies and can be deployed early in the design cycle

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Abstract:

“Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven approach which is data-light and can be adapted anytime in the design process. We verified this methodology across multiple package designs spanning a range of process technology nodes. This methodology is applicable to any heterogeneous integration technology involving multiple dies and can be deployed early in the design cycle.”

Find the technical paper link here.

R. Sankaranarayanan, A. Srinivasan, A. Zaliznyak and S. Mittai, “Chip Package Co-design and Physical Verification for Heterogeneous Integration,” 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 275-279, doi: 10.1109/ISQED51717.2021.9424318. Date Added to IEEE Xplore: 10 May 2021.



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