Big Changes Ahead For Analog Design
By Ed Sperling - 06 Nov, 2024 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of heterogeneous integration on in-house analog tools, and how that is changing the design process, with Mo Faisal, president and CEO of Movellus; Hany Elhak, executive director of product management at Synopsys; Cedric Pujol, product manager at Keysight; and Pradeep Thiagarajan, principal product manager for custom ... » read more

Blog Review: Nov. 6
By Jesse Allen - 06 Nov, 2024 - Comments: 0

Cadence's Satish Kumar C explores how the Deferrable Memory Write transaction type in PCIe and CXL can improve latency, efficiency, and performance by delaying certain memory write operations during system bus congestion or until other priority tasks are complete and highlights implementation and verification challenges. Synopsys' Daryl Seitzer and Rahul Thukral point to magnetoresistive RAM... » read more

Visualization of Photoexcited Charges Moving Across the Interface of Si/Ge
By Technical Paper Link - 05 Nov, 2024 - Comments: 0

A technical paper titled "Imaging hot photocarrier transfer across a semiconductor heterojunction with ultrafast electron microscopy" was published by researchers at UC Santa Barbara and UCLA. "In this work, we apply scanning ultrafast electron microscopy to provide a holistic view of photoexcited charge dynamics in a Si/Ge heterojunction. We find that the built-in potential and the band off... » read more

Energy Storage: Properties of Barium Titanate (Harvey Mudd)
By Technical Paper Link - 05 Nov, 2024 - Comments: 0

A technical paper titled "Understanding surfaces and interfaces in nanocomposites of silicone and barium titanate through experiments and modeling" was published by researchers at Harvey Mudd College, Sandia National Lab and Air Force Research Laboratory. Abstract "Barium titanate (BTO) is a ferroelectric perovskite used in electronics and energy storage systems because of its high dielectr... » read more

Review of Advances in 3D integration of 2D Neuromorphic Electronics, Materials to Systems
By Technical Paper Link - 05 Nov, 2024 - Comments: 0

A new technical paper titled "2D materials-based 3D integration for neuromorphic hardware" was published by researchers at  Seoul National University and University of Southern California. Find the technical paper here. November 2024. Kim, S.J., Lee, HJ., Lee, CH. et al. 2D materials-based 3D integration for neuromorphic hardware. npj 2D Mater Appl 8, 70 (2024). https://doi.org/10.10... » read more

Chip Industry Technical Paper Roundup: Nov. 5
By Linda Christensen - 05 Nov, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=378 /]   Further Reading Chip Industry Week In Review Silicon Valley design center and NY EUV Accelerator; Siemens’ big acquisition; Onto extends panel inspection with two acquisitions; DENSO-Quadric deal; thinner Si-based power wafer; $100M funding for AI; trade wars escalate; earnings rep... » read more

Research Bits: Nov. 5
By Jesse Allen - 05 Nov, 2024 - Comments: 0

Optical in-memory computing Researchers from the University of Pittsburgh, University of California Santa Barbara, University of Cagliari, and Institute of Science Tokyo propose a resonance-based photonic architecture which leverages the non-reciprocal phase shift in magneto-optical materials to implement photonic in-memory computing. “The materials we use in developing these cells have b... » read more

Workload-Specific Data Movements Across AI Workloads in Multi-Chiplet AI Accelerators
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "Next-generation artificial intelligence (AI) workloads are posing challenges of scalability and robustness in terms of execution time due to their intrinsic evolving data-intensive characteris... » read more

Benchmark and Evaluation Framework For Characterizing LLM Performance In Formal Verification (UC Berkeley, Nvidia)
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware" was published by researchers at UC Berkeley and NVIDIA. Abstract "The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital chip design. In particula... » read more

Pre-Silicon Verification Method Addressing Critical Aspects of Speculative Execution Vulnerability Detection
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection" was published by researchers at Technical University of Darmstadt and Texas A&M University. "We introduce Specure, a novel pre-silicon verification method composing hardware fuzzing with Information Flow Tracking (IFT) to address speculative execution leakages. Integrating IFT enables two... » read more

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