Securing Advanced Packaging Supply Chain With Inherent HW Identifiers Using Imaging Techniques
By Technical Paper Link - 14 Oct, 2024 - Comments: 0

A new technical paper titled "Fault-marking: defect-pattern leveraged inherent fingerprinting of advanced IC package with thermoreflectance imaging" was published by researchers at University of Florida and University of Cincinnati. "This work visits the existing challenges and limitations of traditional embedded fingerprinting and watermarking approaches, and proposes the notion of inherent... » read more

UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall
By Ramin Farjadrad - 14 Oct, 2024 - Comments: 0

With the Open Compute Project (OCP) Summit upon us, it’s an appropriate time to talk about chiplet interconnect (in fact the 2024 OCP Summit has a whole day dedicated to the multi-die topic, on October 17). Of particular interest is the Bunch of Wires (BoW) interconnect specification that continues to evolve. At OCP there will be an update and working group looking at version 2.1 of BoW. (... » read more

Chip Industry Technical Paper Roundup: Oct. 14
By Linda Christensen - 14 Oct, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=367 /] More Reading Chip Industry Week In Review AI CPU chiplet platform; Intel-AMD pact; GDDR7 DRAM; AI-RFIC funding; CHIPS Act awards; NoC tiling; thermal modeling on chiplets; $900M nuclear tech and more. Technical Paper Library home » read more

Research Bits: Oct. 14
By Liz Allan - 14 Oct, 2024 - Comments: 0

Si-photonics chip emits beam of light MIT researchers developed a miniature, chip-based “tractor beam” that could help scientists study DNA, classify cells, and investigate the mechanisms of disease. The device uses a beam of light emitted by a silicon-photonics chip to manipulate particles millimeters away from the chip surface, while the sample remains sterile under its glass cover. T... » read more

Improving The Gate Oxide Reliability in Gate First HKMG DRAM Structures (Sungkyunkwan Univ., Samsung)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Novel STI Technology for Enhancing Reliability of High-k/Metal Gate DRAM" was published by researchers at Sungkyunkwan University and Samsung Electronics. Abstract: "The challenges associated with semiconductor are increasing because of the rapid changes in the semiconductor market and the extreme scaling of semiconductors, with some processes reaching their te... » read more

PIO on Current HW Outperforms DMA Over a Range of Payload Sizes In A Number of Different Applications (ETH Zurich)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects" was published by researchers at ETH Zurich. Abstract: "Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers fr... » read more

Survey: HW SW Co-Design Approaches Tailored to LLMs
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models" was published by researchers at Duke University and Johns Hopkins University. Abstract "The rapid development of large language models (LLMs) has significantly transformed the field of artificial intelligence, demonstrating remarkable capabilities in natural language proce... » read more

Chip Industry Week In Review
By The SE Staff - 11 Oct, 2024 - Comments: 0

Imec announced a new automotive chiplet consortium to evaluate which different architectures and packaging technologies are best for automotive applications. Initial members includes Arm, ASE, Cadence, Siemens, Synopsys, Bosch, BMW, Tenstorrent, Valeo, and SiliconAuto. Imec also launched star, a global network bringing together automotive and semiconductor innovators to address technological c... » read more

Confidential Computing: A Key To Secure Cloud And Edge Environments
By Raj Uppala - 10 Oct, 2024 - Comments: 0

Historically, data security was primarily focused on safeguarding data residing within systems controlled by the users themselves, such as on-premise storage and server infrastructure. In such a siloed environment, information stored on the storage media, Data-at-Rest, was encrypted to ensure security. Data-in-Motion (aka Data-in-Transit) was safeguarded by encrypting it before transmitting it ... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe
By Kunal Chhabriya - 10 Oct, 2024 - Comments: 0

Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

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