Machine Learning Tools Accelerate Materials Discovery

By Katherine Derbyshire - 20 Nov, 2025 - Comments: 0

Literature searches, simulations, and practical experiments have been part of the materials science toolkit for decades, but the last few years have seen an explosion of machine learning-driven software tools that promise to accelerate all three. Many of the challenges facing the semiconductor manufacturing industry are fundamentally materials science problems. What metal has the lowest resi... » read more

The Thermal Trap: How Dielectrics Limit Device Performance

By Gregory Haley - 20 Nov, 2025 - Comments: 1

The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

Navigating Geopolitical Shifts And AI-Driven Growth: Insights From The SEMICON West 2025 Market Symposium

By Clark Tseng - 20 Nov, 2025 - Comments: 0

By Clark Tseng and Nishita Rao The 2025 SEMICON West Market Symposium brought together leading analysts and strategists to decode the powerful forces shaping the global semiconductor market. Building on last year’s focus on fabless growth and workforce initiatives, this year’s sessions centered on the rising influence of geopolitics, trade policy, and AI-driven investment. Experts from... » read more

A Decade Of Architectural RowHammer Defense Solutions (Meta, SNU, UIUC)

By Technical Paper Link - 19 Nov, 2025 - Comments: 0

A new technical paper titled "SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms" was published by researchers at Meta, Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "A decade after its academic introduction, RowHammer (RH) remains a moving target that continues to challenge both the industry and aca... » read more

Hardware-in-the-Loop Driving Simulators: Streamlining Integration (Università degli Studi di Firenze)

By Technical Paper Link - 19 Nov, 2025 - Comments: 0

A new technical paper titled "Hardware-in-the-Loop Driving Simulators: Simplifying Real Component Integration in Simulated Environments" was published by researchers at Università degli Studi di Firenze and Meccanica 42. Abstract: "Hardware-in-the-Loop (HiL) driving simulators are valuable tools in assuring efficiency throughout the entire vehicle development and life cycle. Nonetheless, t... » read more

Changes In Mixed-Signal IC Verification

By Ed Sperling - 19 Nov, 2025 - Comments: 0

Analog and digital engineers traditionally have worked in very different worlds. Many analog engineers for years have opted to verify analog designs by scrutinizing waveforms, while digital engineers have treated analog blocks like black boxes. But as these two areas converge in advanced SoCs and multi-die assemblies, the demarcation line between these engineering disciplines is being erased. S... » read more

The Future For Formal Verification

By Brian Bailey - 19 Nov, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss possible future directions for formal verification technology with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemen... » read more

Blog Review: Nov. 19

By Jesse Allen - 19 Nov, 2025 - Comments: 0

Cadence's Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data. Siemens' Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually know... » read more

Intelligence Per Watt: Measuring Local Inference Viability, Studying 20+ Models, 8 HW Accelerators (Stanford Univ.)

By Technical Paper Link - 18 Nov, 2025 - Comments: 0

A new technical paper titled "Intelligence per Watt: Measuring Intelligence Efficiency of Local AI" was published by researchers at Stanford University and Together AI. Abstract: "Large language model (LLM) queries are predominantly processed by frontier models in centralized cloud infrastructure. Rapidly growing demand strains this paradigm, and cloud providers struggle to scale infrastruc... » read more

Research Bits: Nov. 18

By Jesse Allen - 18 Nov, 2025 - Comments: 0

Rubbery CMOS Researchers at University of Illinois Urbana-Champaign, University of Houston, Ulsan National Institute of Science and Technology, Pusan National University, and Southeast University designed fully stretchable complementary integrated circuits composed of both elastic n-type and p-type transistors that provide the same functionality as conventional CMOS while retaining stable elec... » read more

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