Blog Review: Nov. 19

Cadence’s Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data.

Siemens’ Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually known as NonBlocking Assignment, that retains its relevance as one of the most challenging topics for people learning Verilog.

Synopsys’ Hezi Saar and Sajani Patel argue that multi-die designs will be necessary to meet the scalability and performance demands of increasingly complex automotive electronics.

Arm’s David Packwood shows how CPU-based AI inference advances smartphone camera denoising, one of the most critical and computationally demanding steps in the camera pipeline for achieving sharper, cleaner low-light images.

Ansys’ Luke Munholand checks out how computational fluid dynamics tools are being used to test the safety of a quieter supersonic aircraft by determining flight control performance at high angles of attack where a plane can stall.

Keysight’s Anubhab Sahu tries to get LLMs to expose their hidden system prompts by using indirect prompt injection with evasion techniques like writing the prompt in leetspeak, Morse Code, Pig Latin, and ROT13.

In a blog for SEMI, Stanton Chase’s Jan-Bart Smits and David Harap question whether any nation can truly achieve chip self-sufficiency as the semiconductor industry faces pressure to splinter into regional blocks and consider whether disconnecting from the global ecosystem will ultimately hurt competitiveness more than help security.

Plus, check out the blogs featured in the latest Automotive, Security & Emerging Technologies, Test, Measurement & Analytics, and Low Power-High Performance newsletters:

Technology strategy advisor Geoff Tate finds that GenAI value is creating a huge TAM and revenues are ramping at historically fast rates.

Siemens’ Jyothy Jaganathan explains how combining functional fault grading with conventional structural testing improves coverage.

Rambus’ Ajay Kapoor looks at how to safeguard data during computation with hardware-protected enclaves that isolate code and data from untrusted software.

Synopsys’ Markus Stix and Stefan Pruisken find that automotive OEMs and suppliers increasingly are investigating lightweight alternatives to AUTOSAR.

Synaptics guest blogger Nina Turner of IDC posits that openness across software, standards, and silicon is critical for ensuring interoperability, flexibility, and growth.

Keysight’s Jasper van Woudenberg points to the benefits of competition in discovering and patching open-source vulnerabilities.

Infineon’s Sevasti Daneilas looks at using intelligence within tight energy budgets in embedded designs.

Cadence’s Veena Parthan provides a peek inside a new data center facility showcasing the use of digital twins to optimize performance and cost.

Imagination’s Eleanor Brash breaks down how GPUs can deliver a seamless and immersive 360-degree visualization around a vehicle.

PDF Solutions’ Christophe Begue explains why the traditional model of stage-gate, crisis-driven collaboration is reaching its limits.

Siemens’ Lee Harrison points to reliability improvements with the combination of digital twins and silicon lifecycle management.

Modus Test’s Reagan Oliver and Jesse Ko discuss integrating raw power with intelligent mechanical design and operator-focused ergonomics for high-throughput connector testing.

Advantest’s Tadashi Oda looks at the pros and cons of new memory architectures for HPC.

proteanTecs’ Nir Sever examines thermal monitoring improvements in leading-edge chips.

Teradyne’s Ed Seng shows how to adopt new test technologies without disrupting proven workflows.

Fraunhofer IIS/EAS’ Roland Jancke looks at open-source hardware and balancing the benefits provided by community and transparency with the risks posed by capacity and warranty issues.

Rambus’ Lou Ternullo discusses how PCIe retimers enable signal quality across long distances and complex topologies.

Siemens’ Farhad Ahmed examines an effort to shift CDC and RDC verification from a single, time-consuming flat run to a more efficient, distributed, and scalable process.

Synopsys’ James Chuang explains how to compress multiple design scenarios into manageable sets while preserving critical timing information.

Arm’s Martin Weidmann details how upcoming architectural features will extend the ability to detect memory safety violations to more systems and provide application component isolation within a single process.

Cadence’s Kunal Chhabriya shows how PCIe L1 link substates and PHY PIPE states provide granular control over power consumption.

Ansys’ Laura Carter distills information executives shared during a recent event on the early integration of AI, data, models, and simulations, and their impact on design decisions.

Siemens’ Amr Hegazy, Mohamed Abdelkarim, and Reem El Adawi break down a new approach that enhances AI understanding through hierarchical clustering techniques with LLM-driven keyphrase extraction.