Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference" was published by researchers at FZI Research Center for Information Technology and Karlsruhe Institute for Information Technology (KIT). Abstract: "Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural network... » read more

Advantages Of IPL Soldering Over Reflow Soldering For Cu Pillar Bump Interconnections On Glass Substrates (Chungbuk, Sungkyunkwan Univ.)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "Ultrafast Semiconductor Chip Bonding Using Intense Pulsed Light Soldering for Chip-on-Glass Packaging" was published by researchers at Sungkyunkwan University and Chungbuk National University. Abstract: "The increasing demand for miniaturization and improved performance in electronic devices has driven the exploration of glass substrates and advanced soldering ... » read more

Challenges In Testing Photonics In Chips
By Ed Sperling - 21 Nov, 2025 - Comments: 0

The semiconductor industry has spent decades improving reliability and consistency by standardizing when and how to test it, how to collect critical data from those tests, and what to do with that data. But electrical test data is very different from silicon photonics, which is being bundled into these SoCs and multi-die assemblies alongside traditional electrical components. Aftkhar Aslam, CEO... » read more

Chip Industry Week In Review
By The SE Staff - 21 Nov, 2025 - Comments: 0

China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Overcoming BEOL Patterning Challenges At The 3nm Node
By Assawer Soussou - 20 Nov, 2025 - Comments: 0

As complementary metal-oxide semiconductor (CMOS) area shrinks 50% from one node to the next, interconnect critical dimensions (CD) and pitch (or spacing) are under tight demands. At the N3 node, where metal pitch dimensions must be at or below 18 nm,1,2 one of the main interconnect challenges is securing sufficient process margins for CD and edge placement error (EPE). Achieving the... » read more

Advanced Packaging Traceability And Root Cause Analysis
By Aftkhar Aslam - 20 Nov, 2025 - Comments: 0

The semiconductor industry is undergoing a profound transformation. What once centered on single-die silicon packaged in QFN or BGA formats has evolved into a landscape of multi-die integration, chiplets, 3D stacking, and photonics coupling. These advanced packaging architectures are redefining design, manufacturing, and test paradigms—enabling new levels of performance, efficiency, and funct... » read more

Chiplet Integration and Testing: Key Lessons for Next-Gen Semiconductor Packaging
By Vineet Pancholi - 20 Nov, 2025 - Comments: 0

The Chiplet Era Has Arrived The floodgates for chiplet-based design have officially opened. Over the past several quarters, manufacturing test flows have been validating 2.5D package architectures, and production volumes are ramping up. These designs promise flexibility and performance, but they also introduce new test sensitivities—electrical, thermal, and mechanical—that challenge tradit... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets
By Shela Aboud - 20 Nov, 2025 - Comments: 0

When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

New Panel Production Efforts Target Interposer Costs
By Bryon Moyer - 20 Nov, 2025 - Comments: 0

The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

Operator Shortage? Intelligent Machine Vision Can Give More And Better Wafer Inspection
By Errol Akomer - 20 Nov, 2025 - Comments: 0

Right now, wafer manufacturers are having serious problems in finding and retaining operators. And they're desperately looking for ways to keep their fabs running effectively. Fortunately, machine vision can offer a smart solution. To see how it works, let’s first look at the basic fab workflow and check out some opportunities for improvement… How to improve ADI In a typical fab, after... » read more

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