On-Current Performance of Ultra-Scaled NSFETs With Source/Drain Underlap Doping (Global TCAD Solutions, TU Wien)
By Technical Paper Link - 24 Nov, 2025 - Comments: 0

A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. Abstract: "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solutio... » read more

Formal Verification Of Secure Automotive SW Updates (Chalmers, Volvo)
By Technical Paper Link - 24 Nov, 2025 - Comments: 0

A technical paper titled "Towards a Formal Verification of Secure Vehicle Software Updates" was published by researchers at Chalmers University of Technology and Volvo. Abstract "With the rise of software-defined vehicles (SDVs), where software governs most vehicle functions alongside enhanced connectivity, the need for secure software updates has become increasingly critical. Software vuln... » read more

Leveraging NEMS To Address Critical Hardware Security Challenges In Advanced Packaging (U. of Florida)
By Technical Paper Link - 24 Nov, 2025 - Comments: 0

A new technical paper titled "Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging" was published by researchers at University of Florida. Abstract "As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeit... » read more

AI-Driven Collaboration In Chip Manufacturing
By Ed Sperling - 24 Nov, 2025 - Comments: 0

3D chips and multi-die assemblies can offer significant improvements in performance and power, but the tradeoff is the increased amount of time and money it takes to generate working silicon. There are more process steps, more interactions between processes, and more data to manage throughout the manufacturing flow — so much, in fact, that it has now reached well beyond what even the best eng... » read more

PCI Express Design Guide – Q&A for Gen 4, 5, 6
By Cadence - 24 Nov, 2025 - Comments: 0

High-speed PCB design for PCI Express Gen4, Gen5, and Gen6 pushes every dimension of signal integrity and layout engineering. This PCIe Design Guide – Q&A (Part 1) compiles 60 of the most common real-world design questions that engineers face—and provides detailed, practical answers grounded in simulation data, field experience, and compliance testing. Whether you’re defining your... » read more

Faster Bug Discovery And Coverage Closure
By Synopsys - 24 Nov, 2025 - Comments: 0

Modern chip development is a complex process where functional verification often consumes a significant portion of project time and resources. Achieving efficient bug discovery and coverage closure is essential to prevent issues from reaching silicon. This white paper introduces an innovative approach using AI-powered Verification Space Optimization (VSO.ai) to enhance verification processes. ... » read more

Spray And Pray Wastes Power
By Brian Bailey - 24 Nov, 2025 - Comments: 0

For quite some time I have felt that the way the industry approaches power is less than optimal. Techniques such as clock gating and power gating have been used to reduce the amount of unnecessary activity and leakage, but is there more activity that does not contribute to an intended action? While unnecessary activity may be unimportant in the functional sense, it all represents power that ... » read more

IP And Data Management: Challenges, Solutions, And Best-in-Class Approaches
By Keysight - 24 Nov, 2025 - Comments: 0

As electronic design becomes increasingly complex, traditional approaches to IP and design data management are reaching their limits. Fragmented systems, inconsistent documentation, and unclear version control are slowing collaboration, increasing rework, and ultimately constraining innovation. The ability to manage design data effectively is no longer a background concern — it’s a foundati... » read more

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

Emerging Synaptic Memory Technologies For Neuromorphic CIM Platforms (Tampere Univ.)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware" was published by researchers at Tampere University. Abstract: "The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive... » read more

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