Another Brick In The Wall

Economics have always been the foundation of chip development, and they begin to change significantly at 22nm.


The wall is in sight.


Moore’s Law has propelled the semiconductor industry at an amazing velocity since it was first introduced in 1965, and despite some minor changes from 18 months to two years, we have pretty much stayed on course. In the past, most people thought we would hit the wall at 1 micron, and they thought it would happen again at 32nm. The road map appears pretty solid down well beyond that.


But at 22nm—or the half node of 20nm—things seem to get a bit fuzzier than in the past. You can’t just fix one problem anymore. You have to fix a bunch of them simultaneously. And those problems become thornier as you progress down to 10nm. Even the fastest ASICs and processors will begin to look more like systems designs than chips, and designs will expand well beyond the physical limits of the silicon to include software, other components on a board and the manufacturing processes to create them.


This used to be so far in the future that no one really gave it much thought. It was something you talked about over a beer. But with companies now working on 32 nanometer IP blocks and manufacturing processes, it won’t be that long before we start seeing the wall. There will be ways around the wall, of course, but the path will hardly be a straight line.


At the very basic level, lithography technology will have to change. The move to extreme ultraviolet lithography has been talked about for years. TSMC already has committed publicly to immersion lithography. But which way the industry ultimately heads is the subject of lots of research at the moment. So far, there are no clear answers. Both technologies are subject to defects, and while those defects may not be significant at 180nm, they will ruin a chip at 20nm.


On top of that, new transistor designs will be needed. Chip designs already have started going vertical. Memory makers are using stacked die to create their chips. But we’re also starting to see the need for new transistor designs such as FinFETS, which have 3D fins resembling a 1958 Cadillac.


Add to that such technologies as air gap, new materials and substrates such as silicon-on-insulator, and suddenly the wall begins to take shape. From a distance it looks opaque, but up close it’s porous. The only problem is that getting through it requires a huge investment in new technology.


Moore’s Law originally was created as an economic statement of manufacturing economies of scale. The further down the road map, the more the economies of scale begin rolling out in reverse. Many companies have been wondering where the tipping point will be for Moore’s Law, and it varies by company. But the end of the road may be when the last company no longer gets a benefit from putting more transistors on a piece of silicon—no matter what shape they take or how exotic the substrate.


–Ed Sperling



Leave a Reply

(Note: This name will be displayed publicly)