How to address interconnect challenges and reduce wire congestion to achieve design goals.
The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs.
With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce challenges to physical designs, specifically when routing large numbers of wires and meeting clock speed targets.
Find more information here.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply