category: Everything Low Power

category: IoT, Security & Automotive

Low-Power Crisis = Danger & Opportunity
By Brian Fuller - 07 Nov, 2013 - Comments: 0

If you’re a student of these things, you’ve no doubt heard that in Japanese, the word “crisis” is divided equally into “danger” and opportunity.” The biggest opportunity for electronics designers is also their biggest challenge: power management. Ask anyone today and they’ll tell you that minding and managing power consumption and leakage is a big concern. How big? At DAC... » read more

Why Does That App Make My Phone Hot?
By Adam Sherer - 08 Aug, 2013 - Comments: 0

By Adam Sherer Popular Mechanics examined this topic in 2011, focusing mostly on packaging and other physical conditions. “Poor signal, intense workload and battery charging” were quoted, but the verification engineer knows the part of that list that was glossed over—intense workload. The author of that article waved away that aspect, saying the operating system usually can handle the so... » read more

More Efficient Things
By Qi Wang - 11 Jul, 2013 - Comments: 0

By Qi Wang There are many angles to consider when it comes to efficiency and the Internet of Things (IoT). At the architectural level, the IoT system consists of connected things, the networks and the cloud servers for massive data processing. Efficient data storage and servers means lower power consumption, which will result in millions of dollars in savings. For the connected things thems... » read more

Life In A Connected World
By Qi Wang - 13 Jun, 2013 - Comments: 0

By Qi Wang At this year’s DA, we heard a lot of discussions on the Internet of Things. Gregg Lowe, CEO of Freescale, said in his keynote speech that by 2020 there will be 50 billion connected devices. Considering there are an estimated 4 billion devices in the world now, mostly unconnected, this represents huge growth potential for the semiconductor industry because each device will have at ... » read more

Power-Up Low-Power Verification
By Adam Sherer - 09 May, 2013 - Comments: 0

By Adam Sherer When facing low-power verification in the SoC world, everyone could use a few power-ups just like Nintendo’s little plumber, Mario. Sure, Mario could run and jump through a lot of terrain, but when he hit some new challenges he could rely on some new tools and techniques to get him through. Completing your first SoC with a single power control module (PCM) and domain is lik... » read more

CPF 2.0 Voltage Regulator And Analog Ports
By Luke Lang - 08 Nov, 2012 - Comments: 0

By Luke Lang CPF 2.0 was released more than a year and half ago, yet the majority of the designs are still done with CPF 1.1. This is one of those good news/bad news situations. The good news is that CPF 1.1 is perfectly adequate for majority of the LP designs. The bad news is that designers may not be aware of the new CPF 2.0 features that could be quite useful. This month, we will take a loo... » read more

LP Test
By Luke Lang - 11 Oct, 2012 - Comments: 0

By Luke Lang Last month, we discussed testing a portion of a chip at a time to reduce overall power dissipation during test. However, this does not address local power dissipation hotspots that can cause excessive IR drop. These hotspots can occur in regions where many nets are switching at the same time. Typically, a chip’s power grid is designed to meet IR drop specification in the func... » read more

LP Test Strategies
By Luke Lang - 13 Sep, 2012 - Comments: 0

By Luke Lang Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how ... » read more

Power Mode And State
By Luke Lang - 12 Jul, 2012 - Comments: 0

By Luke Lang Low-power designs that use power shutoff (PSO) and multiple-supply voltage (MSV) will have circuits that operate at various voltages, including no voltage. To describe the combination of allowable voltages in a design, CPF uses power mode, and UPF 1.0 uses power state. In CPF, each power mode represents one combination of the states of all power domains. In UPF 1.0, each power ... » read more

LP Macros 2
By Luke Lang - 14 Jun, 2012 - Comments: 0

By Luke Lang Last month, I compared the CPF macro model with LP attributes in the Liberty model. The CPF macro model was developed when Liberty had very little LP attributes to support LP designs. Even today, Liberty still lacks LP attributes to describe some of the common power intent in LP designs. One example is an LP IP block with internal power switches and shutoff domains. Because mos... » read more

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