Save Power And Area By Eliminating Redundant Resets


Resets initialize hardware by forcing it into a known state, either on design start up or to recover from an error. In today’s SoC designs, it is not uncommon to see designs with millions of registers that have resets. Unfortunately, many of these resets are redundant. Leaving these unnecessary register resets in the design leads to increased power consumption, excess area, and routing conges... » read more

Is Low Power Coverage Achievable?


Back in 2005, yes, before the invention of the iPhone, I made a slide to educate users on what to cover in Low Power Verification. Using a simple 3 island test case, I illustrated that verification had to be done in 4 states of operation, with 8 transitions and 16 sequences to be verified. This is after pruning the theoretically possible set of 8 states for on/off voltage islands. More than ... » read more

Evolving LTE Brings New Era Of Connectivity To IoT


The Internet of Things is here and ramping deployment today, but there’s still considerable work underway to optimize many aspects of the network. Not the least of this are the access technologies that exist or are emerging to enable the ‘last mile’ connectivity for IoT connected objects. Wireless access broadly fits into two main areas: licensed band and unlicensed band. Short-range unli... » read more

Three Common SoC Power Management Myths


SoCs are power-sensitive. Sometimes SoCs are sensitive because designers worry about the impact they have on the end product battery life. Sometimes designers worry about the effects of dissipating too much power on packaging and thermal issues. Sometimes designers are simply worried about the massive cooling budgets of data centers generating heat from thousands of their chips running in serve... » read more

Have Margins Outlived Their Usefulness?


To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

Are Models Always The Answer?


Given the shift to system level design and the need to make tradeoffs early in the design process, much emphasis is placed on modeling, and for good reason. Tobias Bjerregaard, CEO of Teklatech reminded that power integrity analysis and signal integrity analysis evolved to be more or less a checkmark from many companies. “They run it and then say, ‘OK, it is fine,’ but they don't think... » read more

Power Integrity Optimization Cuts RF Substrate Noise


Our main focus is on dynamic voltage drop at 16-14-10nm and beyond, but the rise of the Internet of Things (IoT) prompted me to share some silicon measurement results that are relevant to the RF design community. Normally, power integrity (PI) is looked at in the time domain, but in this work we looked at it from a frequency spectrum perspective. Silicon measurements prove how shaping the dynam... » read more

An Introduction To Reducing Dynamic Power


In the past few blogs we have been primarily talking about UPF and applying the Successive Refinement process to save power. But, this process addresses leakage power. In this session we want to talk about how to save dynamic power. As designs move to finFET technology, dynamic power is the dominant contributor to power consumption. Power consumption trend. I recently sat down with my c... » read more

Bluetooth Smart: Doing (A Lot) More With Less


By Charles Dittmer and Prithi Ramakrishnan I was really struck by Ann Steffora Mutschler's piece last month (Running Out Of Energy?). She notes that by 2040, the energy required for computing is expected to surpass the estimated world's energy production. That's a problem. One factor could be the rise of IoT applications. Billions of devices will be deployed in the next decade, and we ... » read more

Using Multi-Channel Connections for Optimized LPDDR4 Power & Performance


LPDDR4, the latest double data rate synchronous DRAM for mobile applications, includes a number of features that enable SoC design teams to reduce power consumption of discrete DRAM in mobile devices. Desktop devices like PCs and servers commonly utilize DDR devices mounted on dual inline memory modules (DIMM) hosted on 64-bit wide buses. This board-level solution allows field-upgradeable DRAM ... » read more

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