Watch Out For 200mm Fabs: Fab Outlook To 2020


One year after the debut of the industry’s first 200mm Fab Outlook report, SEMI has just issued an October 2016 update with the improved and expanded report forecasting 200mm fab trends out to 2020. This extensive report features trends from 2009 to 2020, showing how 200mm fab activities and capacity change worldwide.  Industry spending for construction and equipment is detailed and analy... » read more

IP Market: CPU Still The Largest But Security Leads In Growth


The 3rd Party Semiconductor Intellectual Property (SIP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures that the entire electronics market has undergone, it is the 3rd Party SIP market. Most of these evolutionary forces are dr... » read more

How Many Nanometers?


What’s the difference between a 10nm and a 7nm chip? That should be a straightforward question. Math, after all, is the only pure science. But as it turns out, the answer is hardly science—even if it is all about numbers. Put in perspective, at 65nm, companies defined the process node by the half pitch of the first metal layer. At 40/45nm, with the cost and difficulty of developing n... » read more

Achieving The Vision Of Silicon Photonics Processing


With the increasing need for faster data transfer rates, the transition from electrical to optical signaling in data processing is inevitable. Copper cabling cannot keep up with the upcoming data center bandwidth requirements for applications such as multimedia streaming and high performance computing. One technology that could enable true optical communication is silicon photonics. Silicon is ... » read more

Creating An Accurate FEOL CMP Model


By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

Will GPU-Acceleration Mean The End Of Empirical Mask Models?


Shrinking mask feature sizes and increasing proximity effects are driving the adoption of simulation-based mask processing. Empirical models have been most widely used to date, because they are faster to simulate. Today, GPU-acceleration is enabling fast simulation using physical models. Does the ability of GPU-acceleration to make physical models a practical solution mean the end of empirical ... » read more

China Ramps Up Power IC Manufacturing


In addition to changes in power devices being implemented to meet market trends that I discussed in previous posts, there are significant shifts taking place in the locations where these components are manufactured. Over the past 10 years, we’ve seen an increase in power device manufacturing in China, Europe and South East Asia and a subsequent drop off in North America. If we look at ... » read more

What To Do With A GaN PDK


Wolfspeed's Jeremy Fisher provides a hands on demo of how his group achieved a first-pass run of a 40GHz MMIC chip using using a PDK for its 0.14 micron process. [youtube vid=i7dsQG8CTO4] » read more

Smartphone Security: For Your Eyes Only


Fans of the Olympics here in the United States were treated to a great Samsung commercial throughout the broadcast. The commercial stars the genius, multi-award-winning actor Christoph Waltz, showing how Americans can multitask with the amazing new Galaxy Note7. Yes, THAT Galaxy Note7. The 90-second long commercial is a delight to watch, but it must have cost Samsung some serious bucks to produ... » read more

450mm And Other Emergency Measures


Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

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