The Next Materials Race


Trade wars are costly on many fronts, and a trade war between the United States and China is bound to cause a variety of problems that no one anticipated. But in some areas, there may be a silver lining. And where there is no silver lining available, other materials may suffice. For decades, big chipmakers have been squeezing the entire semiconductor supply chain in a race to double the num... » read more

Love and Affection in the Age of Robots


It is increasingly common to rely upon robotic devices to perform a wide range of tasks that were previously handled by humans. With robots becoming more pervasive in our lives, people are demonstrating a tendency to treat and relate to robot assistants as they would their pets and loved ones. We are beginning to project companion status on these mechanical tools. There is ample evidence tha... » read more

Virtual Packages Improve Signal Integrity


The 112 Gb/s generation of SerDes has brought along excessive loss within the package, around 5 dBs of loss within each monolithic package. This loss markedly reduces the usefulness of these SerDes. MCM technology has progressed to where the use of 70mm packages is routine. Non-interposer MCMs easily can use 20 or more chiplets, plus large dies and passives can be used. These MCMs have low ... » read more

SerDes For Chiplets


The XSR 56G and 112G Interoperability Agreements (IAs) announced by the OIF are intended to cover a channel consisting of a pair of up to 50mm. The primary defined application of the XSR SerDes is connecting a chip to a “nearby” optical engine. Because the requirements on these channels are much less stringent than they are on long reach channels, XSR SerDes are expected to have lower power... » read more

Why Test Costs Will Increase


The economics of test are under siege. Long seen as a necessary but rather mundane step in ensuring chip quality, or a way of testing circuitry from the inside while it is still in use, manufacturers and design teams have paid little attention to this part of the design-through-manufacturing flow. But problems have been building for some time in three separate areas, and they could have a b... » read more

Collaboration And Advanced Substrates


Discussions of semiconductor manufacturing tend to focus on CMOS logic and memory devices, sometimes to the exclusion of everything else. Discussions of silicon-on-insulator wafer markets focus on the needs of high performance logic. Lithography analysts emphasize high density memories. It’s easy to forget that real systems contain other devices, too. A modern smartphone probably supports ... » read more

How Much Data Can Be Pushed Through Copper Wires?


As the amount of digital data grows, so do requirements on the speed of the transmission at all levels of the transmission chain—between dies in a shared package, between packaged chips inside a device, and between devices. The communication channels encountered at every stage of this communication are different in nature. Those between dies in a shared package, or between packaged chips in a... » read more

Thinking Ahead To Society 5.0


Industry 4.0 is a familiar term throughout the global semiconductor community. It conjures images of fully automated factories and computerized decision making at all levels of business. Less widely known is Japan’s thinking about the next step in technological evolution, which it calls Society 5.0. Instead of viewing upcoming technology advances as the fourth industrial revolution, Japan tak... » read more

The Quest For Perfection


Demands by automakers for zero defects over 15 years are absurd, particularly when it comes to 10/7nm AI systems that will be the brains of autonomous and assisted driving or any mobile electronic device. There are several reasons for this. To begin with, no one has ever used a 10/7nm device under extreme conditions for any length of time. Chips developed at these nodes are just starting to ... » read more

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science


Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration. Often, with these new advanced solutions come challenges that can impact ... » read more

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