category: Building The IoE

category: Auto, Security & Edge AI

Reduce Memory Redesigns With Shift-Left
By Chun-hsiang Chang - 05 Jun, 2026 - Comments: 0

Engineering managers overseeing memory design know the pattern well: a promising architecture moves smoothly through schematic capture and into layout, only to stumble when integration testing reveals contention issues that force expensive redesigns. Address decoders that looked correct in isolation turn out to enable multiple banks simultaneously. Power switches configured for aggressive gatin... » read more

Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity
By Muhammad Hassan - 07 May, 2026 - Comments: 0

By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration. Fig. 1: 3D-IC and 2.5D structure. These architectures are essential to meeting the extreme performance and bandwidth demands... » read more

Automated Multiphysics For Successful 3D-IC Design
By John Ferguson - 02 Apr, 2026 - Comments: 0

By John Ferguson and Sheltha Nolke For design teams adopting 3D-IC architectures, the relentless pursuit of performance and reliability brings a familiar, yet increasingly complex, set of challenges: how do we manage power, dissipate heat and navigate the intricate dance of physics within these stacked architectures? While 3D-ICs offer significant advantages in size, performance, power effic... » read more

Across The Vast Reaches Of The 3D Stack: Mastering ESD Verification In Advanced Semiconductor Design
By Keerthana Chelur Hithesh - 05 Mar, 2026 - Comments: 0

Introduction: The epic challenge In the vast reaches of the semiconductor cosmos, a silent menace lurks—one that can obliterate years of design work in a fraction of a nanosecond. Electrostatic discharge (ESD) verification stands as the guardian against this invisible threat, a critical discipline that separates the triumphant chip designs from the smoldering wreckage of failed silicon dream... » read more

Six 3D-IC Design Trends That Secure The AI Era
By Pratyush Kamal - 05 Feb, 2026 - Comments: 0

By Pratyush Kamal and Todd Burkholder Greater functionality, performance, and speed are in great demand in pervasive computing, RF, and automotive electronic systems, as well as most everything else. Complexity continues to skyrocket, leading many to say we are officially in the post-Moore’s Law world. In his seminal 1965 paper, “Cramming more components onto integrated circuits,�... » read more

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL
By Vlada Kalinic - 08 Jan, 2026 - Comments: 0

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Securing The Design Journey
By Matt Walsh - 04 Dec, 2025 - Comments: 0

In automotive, security, and pervasive computing, the stakes of failure have never been higher. Functional safety, security compliance, long product lifecycles, and system resilience are no longer differentiators — they are baseline requirements. Yet many semiconductor and system companies are still relying on an outdated engagement model built around static datasheets, fragmented tools, and ... » read more

Integrating Design Verification To Approach Zero Defects
By Jyothy Jaganathan - 06 Nov, 2025 - Comments: 0

As semiconductor applications in automotive, data center, and high-performance computing grow increasingly mission-critical, the industry faces mounting pressure to achieve near-perfect manufacturing test coverage—often exceeding 99%. Yet, meeting stringent zero-defect defective parts per million (DPPM) targets remains a formidable challenge. Traditional structural testing methods frequently ... » read more

Unearthing Hidden Reliability Risks
By Matthew Hogan - 09 Oct, 2025 - Comments: 0

Successful automotive electronic design requires a focus on safety, performance and customer satisfaction. This makes IC reliability not just a “nice to have” feature, but a fundamental requirement. From advanced driver-assistance systems (ADAS) to infotainment and powertrain controls, every IC must work with exceptional reliability, even in tough conditions. Imagine a tiny circuit flaw in ... » read more

Navigating Reliability Potholes: Early 3D Stress Analysis For Automotive ICs
By Shetha Nolke - 04 Sep, 2025 - Comments: 0

The rise of 3D integrated circuits (ICs) and heterogeneous packaging is reshaping how automotive ICs fulfill demanding analog and sensor requirements. Whether for radar, lidar, sensor fusion or domain controllers, advanced packaging enables new levels of integration—and performance—in automotive electronics. Yet, as these architectures grow more complex, they also introduce new forms of mec... » read more

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