How To Optimize Silicon Utilization To Improve PPA


In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce ... » read more

Data Movement Is the Energy Bottleneck of Today’s SoCs


In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). The efficiency of data movement across the chip has become just as important. Whether designed for data centers or edge AI devices, SoCs must now prioritize data transport as a core architectural consideration. Moving data efficiently across the silicon f... » read more

AI-Driven Verification Regression Management


By Paul Carzola and Taruna Reddy Coping with the endless growth in chip size and complexity requires innovative electronic design automation (EDA) solutions at every stage of the development process. Better algorithms, increased parallelism, higher levels of abstraction, execution on graphics processing units (GPUs), and use of AI and machine learning (ML) all contribute to these solutions. ... » read more

Reap Rewards With Shift-Left Pattern Matching For Custom And AMS Designs


To keep up with the growing complexities of IC design, major semiconductor companies are adopting shift-left strategies. For verification, this means pulling much of the work into the physical design stage. By moving critical checks earlier in the design cycle, you can identify and resolve issues before they escalate, streamlining the overall development process. The Calibre tools have been ... » read more

NOP Flit Payload: A Dedicated Debug Channel


Modern PCIe systems are complex, with high-speed data transfer and intricate protocols. Traditional debug methods often struggle to provide the necessary granularity and real-time visibility into link behavior. Transient issues, timing-sensitive errors, and protocol interactions can be difficult to pinpoint with conventional methodology. NOP Flit addresses this challenge. PCIe Gen 6 introduc... » read more

What Is Electronic Design Automation And Why Do You Need It?


As data speeds push into the multi-gigabit range and requirements on digital systems grow more complex, cutting down the time-to-market while also ensuring error-free reliable designs seems impossible. Traditional design tools and practices can result in failed prototypes, costly respins, delayed time-to-market, missed market opportunities, and subpar performance. This is why advanced EDA to... » read more

How AI And Connected Workflows Will Close The Verification Bottleneck


For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into the bottleneck of development cycles. This challenge has a name: Verification Productivity Gap 2.0. Back in the early 2000s, the Verification Productivity Gap 1.0 emerged when design complexi... » read more

High-Speed High-Capacity Mixed-Signal Simulation Of Silicon Photonics


Many of today’s computing and communications applications demand almost unimaginable processing capability and high-bandwidth access to memory. For example, many data center systems using high-end Graphics Processing Units (GPUs) often need to transfer multiple terabytes per second. Traditional copper-based interconnects, limited to speeds of hundreds of megabits per second (Mbps), cannot ... » read more

Unleashing AI Potential Through Advanced Chiplet Architectures


The rapid proliferation of machine-generated data is driving unprecedented demand for scalable AI infrastructure, placing extreme pressure on compute and connectivity within data centers. As the power requirements and carbon footprint of AI workloads rise, there is a critical need for efficient, high-performance hardware solutions to meet growing demands. Traditional monolithic ICs will not sca... » read more

Innovating For 6G


As the world eagerly anticipates the arrival of applicable 6G innovations, researchers face numerous challenges in validating this next-generation wireless communication technology. The journey from theoretical concepts and mathematical equations to real-world 6G implementation is complex and requires meticulous planning, testing, and measurements to better characterize these ultra-high freque... » read more

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