Getting A Standard Right The First Time


The development of standards is a tricky balance, especially when going into areas that are nascent. The [getentity id="22863" e_name="Portable Stimulus Standard"] (PSS), being developed within [getentity id="22028" e_name="Accellera"] is one of those. This could be the most important standard since [gettech id="31017" comment="Verilog"] and [gettech id="31040" comment="VHDL"]. And if there ... » read more

Generically Reusable IP No One Uses


I can’t tell you how many times this line has jumped into my mind over the last couple decades, probably because I lost count sometime in 1998... Manager: “...why do they put a guarantee on the box then?” Tommy: “‘Cause they know all they sold you was a guaranteed piece of s***.” That’s an exchange from the movie Tommy Boy, a classic from my university days. Tommy Callaha... » read more

Thinking Much Bigger


For the better part of the past decade the focus has been on integrating an increasing number of smaller components on a piece of silicon. It's time to start thinking much bigger. While there is still plenty of work to be done building more powerful processors, or networks of connected processors on a chip or in a package, new opportunities are opening up in markets such as automotive, medic... » read more

System Design And Verification Challenges: Are They On- Or Off-Chip?


What are the next natural items for mobile devices to be integrated? From 2002 to today, previously separate items (like GPS, cameras and keyboards) have been integrated into the phone. They caused a frenzy of integration within systems on chips. Now we have the Internet of Things (IoT) adding a trillion devices to the picture. Which ones are to be integrated, if any? What does all this mean fo... » read more

Get To Know The Gate-Level Power Aware Simulation


The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

Prototyping Building Blocks


Lego has existed for 85 years. The company was founded August 10, 1932, and after all these years, the concept of building structures big and small still hasn’t lost any of its charm. For my children, now 10 and 12, it is probably the most played with toy throughout their childhood. As with any new purchase, they initially and carefully build the specific design for the instructions included ... » read more

Finite State Machine Synthesis In Programmable Circuits


Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions? For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology. C... » read more

Making Software Development Equivalent For Models And Boards


Selected Cortex-M processors include the instruction trace microcell (ITM) to help understand system behavior. Although it can provide other types of trace, the ITM is commonly associated with printf() output and event tracing from applications and operating systems. Historically, Fast Model systems have used semihosting or UART models to provide character and file I/O when running software on ... » read more

Talking The Talk On Training


In my prior post, I discussed the value of good design flow training. A properly executed program can turn average engineers into above average problem solvers with the right tools and techniques. We got to thinking about this opportunity quite seriously at eSilicon. Is there a way to develop a focused, intense training program to create a new “army” of elite designers? In short, we thin... » read more

DVCon Europe Takes Over Munich October 16-17


DVCon Europe is on the horizon, and this year's program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based De... » read more

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