Interface DRC Can Streamline Chip-Level Interface Physical Verification


In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

Neural Nets In ADAS And Autonomous Driving SoC Designs


Automotive electronics has ushered in a new wave of semiconductor design innovation and one new technology gaining a lot of attention is neural networks (NNs). Advanced driving assistance systems (ADAS) and autonomous car designs now rely on NNs to meet the real-time requirements of complex object-recognition algorithms. The concept of NNs has been around since World War II, promising a futu... » read more

Bugs With Long Tails Can Be Costly Pests


I don’t think Van Gogh was considering high performance computing or server architecture, but he made a lot of sense when he said "great things are done by a series of small things brought together." A series of very small things can, and do, create big things: that’s the fundamental premise of long-tail marketing: Amazon, for one has built a strong business from selling millions of niche i... » read more

Inside UVM, Take Three


The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Why Your FPGA Synthesis Flow Requires Verification


When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

Deep Learning And The Future


Following up from my last post on our deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation,” I’d like to take a glimpse into the future. Like many such discussions, it’s often useful to take a look back first to try and make sense out of what is to come.  That’s essentlially what our keynote speaker, Ty Garibay, did at the event. Ty is the CTO... » read more

Design Flows At 5nm And Beyond


It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40 nanometers was the most advanced node that I ever designed SoCs at and, although it wasn’t easy back then, it pales against the myriad of challenges facing designers today. Back then, compartmentalization of function and roles was relatively easy. We do ... » read more

Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018


Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, a... » read more

Looking For The Elephant In The Valley


As a new arrival in the Silicon Valley and a woman, my head is full of statistics and charts. Not the kind that data scientists use to power their decision-making, but the kind that has made its way into the public discourse more and more in the last few years—diversity numbers in the tech industry. Armed with this data, I set out to talk to my company’s female CEO, Sundari Mitra, as wel... » read more

Abstracting Abstracter Abstractions In Functional Verification


I heard a clear three-part message during DVCon at the end of February: verification engineers must abstractly embrace the abstract idea of abstracting abstract abstraction through higher levels of abstraction; we overuse the word abstract to emphasize the value of whatever verification technique we happen to be talking about; and the key to new abstractions is using Portable Stimulu... » read more

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