category: Blogs – SLD

category: IoT, Security & Automotive

Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
By Nilesh Kamdar - 02 Jul, 2025 - Comments: 0

After 26 years in the electronics industry, I've witnessed countless technological shifts, but few have been as transformative — or as promising — as what we're experiencing with the CHIPS Act. I spoke at a recent 62nd DAC panel discussion alongside industry colleagues Saverio Fazzari from Booz Allen Hamilton and Vivek Prasad from a non-profit organization established to operate the Nationa... » read more

Rethinking Chip Debug
By Priyank Jain - 30 Jun, 2025 - Comments: 0

The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, greater integration and larger silicon areas—the established debug strategies are breaking under the weight of scale. Today’s advanced chips can generate an overwhelming number of design rul... » read more

Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures
By Moshiko Emmer - 26 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data,... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 26 Jun, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Mastering Chiplet Design
By Michelle Clancy Fuller - 03 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a fundamental shift from monolithic chip designs to chiplet-based architectures. This modular approach promises enhanced performance, cost efficiency, and scalability, but it also brings unique system-level verification challenges that design teams must overcome. Chiplet systems break different functions into smaller, separate dies, improving yield an... » read more

Accelerating Scalable Computing
By Shivi Arora - 02 Jun, 2025 - Comments: 0

By Shivi Arora and Sue Hung Fung As computing demands for HPC, AI/ML, and cloud infrastructure grow, modular architectures are replacing traditional monolithic System-on-Chip (SoC) designs. These legacy designs are increasingly expensive and difficult to scale due to ever-increasing silicon complexity. In response, the industry is embracing chiplet-based System-in-Package (SiP) solutions,... » read more

Addressing Stress In Heterogeneous 3D-IC Designs
By Shetha Nolke - 29 May, 2025 - Comments: 0

The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Closing The RISC-V Verification Disconnect
By Larry Lapides - 29 May, 2025 - Comments: 0

With the explosive adoption of RISC-V processors, processor verification has become a hot topic. This is due both to the criticality of the processor IP in the SoC and to the fact that many experienced SoC verification engineers are doing their first processor verification project. While there are similarities between SoC verification and processor verification, there are also significant diffe... » read more

Boosting AI Performance With CXL
By Vanessa Do - 29 May, 2025 - Comments: 0

As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions – or even trillions – of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training. Hence, there is a constant demand for flexible memory expansion and memory sharing among d... » read more

CSR Management: Life Beyond Spreadsheets
By Insaf Meliane - 29 May, 2025 - Comments: 0

The ASIC, ASSP, and system-on-chip (SoC) design landscape has undergone significant evolution over the past two decades. For example, while early devices contained only tens of intellectual property (IP) blocks, modern high-end SoCs may integrate up to 1000 IPs, each containing millions of logic gates. Furthermore, unlike their predecessors, today’s SoCs are no longer primarily hardware; i... » read more

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