Ensuring Your Power And Ground Nets Are Correctly Connected


In most chip designs, the power and ground nets are likely your largest and most important nets. If any devices are not properly connected, then you cannot expect them to function as expected. Amongst the many problems that can occur to power and ground involves the connections to the well areas of your design that power all the bulk connections to your devices. Well regions connectivity is oft... » read more

DAC Panel Could Spark Fireworks


Panels can often become love fests. While a title may sound controversial, it turns out that everyone quickly finds that all the panelists agree on the major points. This is sometimes the result of how the panel was put together – the proposal came from one company, and they wanted to get their customers or clients onto the panel. They are unlikely to ask a major competitor to be part of the ... » read more

Vision Is Why LLMs Matter On The Edge


Large Language Models (LLMs) have taken the world by storm since the 2017 Transformers paper, but pushing them to the edge has proved problematic. Just this year, Google had to revise its plans to roll out Gemini Nano on all new Pixel models — the down-spec’d hardware options proved unable to host the model as part of a positive user experience. But the implementation of language-focused mo... » read more

Turbocharging Cost-Conscious SoCs With Cache


Some design teams creating system-on-chip (SoC) devices are fortunate to work with the latest and greatest technology nodes coupled with a largely unconstrained budget for acquiring intellectual property (IP) blocks from trusted third-party vendors. However, many engineers are not so privileged. For every “spare no expense” project, there are a thousand “do the best you can with a limited... » read more

AI-Powered Data Analytics To Revolutionize The Semiconductor Industry


In the age where data reigns supreme, the semiconductor industry stands on the cusp of revolutionary change, redefining complexity and productivity through a lens crafted by artificial intelligence (AI). The intersection of AI and the semiconductor industry is not merely an emerging trend—it is the fulcrum upon which the next generation of technological innovation balances. Semiconductor comp... » read more

Embracing The Future: 5G NTN – Satellite Service For The Masses


In a world where communication is paramount, access to reliable networks is not just a luxury but a necessity. Traditionally, satellite communications have been reserved for specialized terminals with cumbersome antennas and costly subscription plans. However, with the advent of 5G Non-Terrestrial Networks (NTNs), the landscape of satellite phone availability is undergoing a revolutionary tran... » read more

AI Accelerated Migration Of Existing Designs To New Processors


In this fast-paced digital age where speed, performance, and time-to-market are king, chip designers are under pressure to deliver high-performance computing that doesn’t compromise power efficiency. The constant demand for instantaneous data processing and sharing is pushing the boundaries of innovation in chip design. With this context, we revisit and revamp the insights from the Synopsys U... » read more

Revitalizing DAC


The 61st Design Automation Conference is just two months away and as I get closer to retirement, I know there will only be a few remaining for me. I entered the EDA industry in 1980, so have been involved with it for almost 45 years. Over that period, I have only missed a few. It is interesting how the conference has changed over the years. In the early days, DAC was only a conference, where... » read more

The 3D-IC Multiphysics Challenge Dictates A Shift-Left Strategy


As the industry marches forward in a 3D-IC centric design approach (figure 1), we are facing a new problem. Sometimes referred to as “electro-thermal” or “electro-thermo-mechanical,” it really is the confluence of multiple forms of physics exerting impacts on both the physical manufacture and structure of these multi-die designs and their electrical behavior. Fig. 1: Illustration... » read more

Verification In Crisis


Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been improving overall, as has the complexity of designs. For ASICs, 74% of the designs surveyed in the recent Wilson Research Group/Siemens EDA report have one or more processor cores, 52% have two or mor... » read more

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