IP Subsystems Are Nothing New

By Kurt Shuler - 28 Apr, 2011 - Comments: 0

By Kurt Shuler I’ve been hearing the term “IP subsystem” lately, and it seems to be the latest newfangled buzz word in the SoC semiconductor and IP industry, second only to “virtualization.” Much of the context for this growing interest in IP subsystems has been inspired from the work of Rich Wawrzyniak in his Semico Research report, “IP Subsystems: The Next IP Market Paradigm - Oc... » read more

Interchip Connectivity

By Kurt Shuler - 31 Mar, 2011 - Comments: 0

By Kurt Shuler There has been a lot of confusion about the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned. Why interchip connectivit... » read more

Semiconductor M&A?

By Kurt Shuler - 24 Feb, 2011 - Comments: 0

Last week a friend of mine was giddy with joy as he exclaimed, “Semi M&A is back!” It seems Qualcomm’s acquisition of Atheros and Intel’s acquisition of Silicon Hive somehow changed the chemical makeup of his brain, transforming him from an eternal semiconductor market pessimist to a born-again optimist. Being someone who lives and dies by data, my initial response was, “Let’s s... » read more

Missing The Point

By Kurt Shuler - 27 Jan, 2011 - Comments: 0

By Kurt Shuler A couple months ago a professor researching in my company’s technology space asked me, “Why doesn’t industry use our research?” I thought for a few seconds, then looked him in the eye: “Because much of it is off target.” My friend was taken aback for a second, but to his credit he wanted to know why I thought that. I explained that I recently read an articl... » read more

Is An FPGA IP Business Model Finally Possible?

By Kurt Shuler - 16 Dec, 2010 - Comments: 0

By Kurt Shuler The IP-SoC conference panel, “IPs on FPGA: Strategy and Vision,” was a learning experience for me. Coming from the software and silicon/ASIC/ASSP worlds, I thought I had a pretty comprehensive view of all the various IP licensing models and their technical implementations. But I learned something new that makes me feel positive about the FPGA’s abilities to finally offer a... » read more

Behind The Standards

By Kurt Shuler - 18 Nov, 2010 - Comments: 0

By Kurt Shuler As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there's much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transacti... » read more

NoC Is Not A Noun

By Kurt Shuler - 23 Sep, 2010 - Comments: 0

By Kurt Shuler Today in the IP and EDA business, I hear “knock” all the time, except people mean “NoC.” It seems everybody wants a NoC, or wants to offer you a NoC. I’m here to tell you that NoC is not a noun. A network-on-chip is a technology approach that can be used to transfer data and commands in many domains. When people in the IP and EDA businesses say NoC, they are usually... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: NoC NoC