Building In Functional Safety At The Lowest Hardware Levels Supports Autonomous Driving’s Future

By Kurt Shuler - 27 Dec, 2017 - Comments: 0

Long before automotive electronic system designers chose artificial intelligence and machine learning as the path toward the future of autonomous driving’s future, it was clear that high-performance computing platforms typically found in data center systems clearly were not going to provide all the answers. Automotive system designers place more emphasis on functional safety and resilience, w... » read more

Heterogeneous Cache Coherence Requires A Common Internal Protocol

By Kurt Shuler - 30 Nov, 2017 - Comments: 0

Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and complexity, it becomes too difficult to manage data flow solely through software means. An approach that simplifies software while improving performance and power consumption is to implement hardware... » read more

ADAS Design Shifts Toward Hardware

By Kurt Shuler - 30 Oct, 2017 - Comments: 0

Autonomous driving will challenge system-level designers like never before with the simultaneous integration of three critical areas: Supercomputing complexity, real-time embedded performance, and functional safety. To get there, developers will need to shift their focus from a software-centric approach toward custom hardware development to produce a system that meets the safety, cost, and powe... » read more

Avoiding Traffic Jams In SoC Design

By Kurt Shuler - 28 Aug, 2017 - Comments: 0

While sitting in a traffic jam on the way to work, I realized that the sheer volume of vehicles on the road exceeds the capacity originally planned for by civil engineers, when highways first hit the drawing boards 50 or 60 years ago. It dawned on me that there is a parallel to today’s System-on-Chip design—engineers are struggling to close timing on the interconnect during the back-end pla... » read more

Reducing Latency In ADAS SoC Design Enhances QoS For Digital Mirroring

By Kurt Shuler - 27 Jul, 2017 - Comments: 0

The state-of-the-art of Advanced Driver Assistance Systems (ADAS) is quickly changing, and ADAS chip engineers are finding that on-chip quality-of-service (QoS) is becoming a system-level constraint on ADAS performance. Designers need innovative approaches to address these issues, which is why Dream Chip Technologies highlighted one such method in a recent presentation. Dream Chip Technologi... » read more

Toward Better Accelerators

By Kurt Shuler - 03 Jul, 2017 - Comments: 0

In the not-too-distant past, the standard mobile application processor architecture was the predominant one used for most System-on-Chip (SoC) designs, but that is rapidly changing as new systems and applications emerge in the post-mobile computing era. New requirements for autonomous driving are motivating technology innovations: Visual processing, deep neural networks and machine learning pla... » read more

ISO 26262 Functional Safety Training Resources

By Kurt Shuler - 22 Dec, 2016 - Comments: 0

The automobile has taken over the mobile phone’s pole position as the driver of new semiconductor technologies, like machine learning and vision processing. As a result, many electrical engineers in the semiconductor industry are finding themselves in a state of transition where their current skills, education, and experience are not sufficient for them to achieve the kind of role they would ... » read more

Early Power Modeling Using SystemC And TSMC System-PPA

By Kurt Shuler - 10 Oct, 2016 - Comments: 0

Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance

By Kurt Shuler - 25 Aug, 2016 - Comments: 0

Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

USDOT Smart City Challenge: Columbus Drives Future of Automotive Semiconductor Development

By Kurt Shuler - 05 Jul, 2016 - Comments: 0

The Smart City Challenge will be an accelerant of automotive semiconductor innovation. The U.S. Department of Transportation has chosen Columbus as the winner of the Smart City Challenge, entitling Ohio’s capital city to $40 million U.S. government funding, along with $10M from Paul Allen’s Vulcan investment firm, and $90M that Columbus raised from private partners, to create a fully integr... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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