How SoC Interconnect Enables Flexible Architecture For ADAS And Autonomous Car Designs

More sophisticated automotive chips call for a more advanced methodology to stitch together IP.


When the mobile phone era saw its fastest growth, the design teams that were the most innovative were able to introduce game-changing features before anyone else. Those companies also had the most configurable interconnect IP, allowing them to adapt to quickly changing market needs faster than their competition.

Now, nearly a decade later, when autonomous driving is quickly moving into the mainstream, the semiconductor industry must evolve at a rapid pace to innovate in more efficient means of processing huge amounts of data, for instance, by using machine learning and neural network hardware accelerators. And they must design functional safety into automotive systems at the lowest possible level.

Automotive SoC design methodologies are also changing because of the level of complexity required: The average number of IP cores integrated into automotive SoCs is growing from nearly 20 about five years ago to more than 100 within the next few years. This level of complexity is being created by two trends. First, multiple functions that used to be performed by many discreet microcontrollers are now being consolidated onto a single SoC. I call this “computational consolidation.”

Second, the desire for safer and more autonomous vehicles is driving the creation of supercomputer-like chips that take in vast amounts of information, make decisions, and instigate physical actions in near real-time. These SoCs in the automotive market are now gaining differentiation through their architectures, because they are assembled out of a relatively common mixture of internally-developed and commercial IP functions or blocks.

This trend is also making an impact on the semiconductor IP providers who offer the functional “ingredients” that make up a chip. The need for more sophisticated chips calls for a more advanced methodology to stitch together all the intellectual property, to enhance on-chip communications, to help ensure functional safety, and to provide designers with greater control of power management and silicon-die area optimization.

Here is a sneak peek into what’s driving the innovation in automotive computing platforms, and how interconnect IP helps chip designers create flexible architectures to figure out what must fit into their SoCs for advanced driver assistance systems (ADAS) and autonomous vehicles.

Changing face of automotive SoCs
While the majority of the IP blocks are proven, established, and not very configurable, it is the interconnect IP that must adapt to chip requirements and, in essence, implements the SoC architecture. And it’s revised many times during a chip project as requirements and implementation decisions change, and these changes to the interconnect require changes in quality-of-service, security and safety configurations to optimize the overall system.

Some of the new application areas for automotive SoCs include ADAS, sensor fusion for autonomous driving, vision processing (front camera, object detection, and recognition, surround view, etc.), advanced sensor control and processing (LIDAR, RADAR, etc.) and machine learning for decision making functions in all these domains.

While many of these applications will evolve from previous generations, others will require new chip architectures to address the need for high-performance computing in a small, cost- and power-efficient form factor.

Fig. 1: Automotive SoC and electronic system designers turn toward more advanced SoC infrastructure to surmount the challenges presented by automotive system design. Source: Arteris IP

And for the new architectures that implement these applications, it is mission critical for automotive SoC design teams to have the most efficient, highest performance, and cost-effective interconnect IP as the on-chip communications backbone of their designs.

The case for functional safety
The consumer expectation of automated highway driving is reasonably close to wide-scale acceptance. Some companies even feel confident enough that they are proposing the introduction of urban robo-taxis as early as next year.

Take Lyft, for instance, which offered free robo-taxi rides at the CES 2018 technology showcase in Las Vegas. The demo vehicles included a safety driver and an engineer ready to take over if something went wrong. However, accidents caused by poorly designed electronic systems in truly driverless vehicles could create negative publicity that might slow down consumer acceptance of these new technologies.

The automation-assisted vehicle consists of very complex mission-critical systems that must work as well as we can possibly make them to ensure safety. New generations of “supercomputers-on-a-chip” are being designed to control these multi-thousand-pound vehicles, and as a result, semiconductor IP companies have to deliver technology that supports not only the awesome functional goals of semiconductor vendors but also their safety goals.

Fig. 2: A view of how interconnect IP like network-on-chip (NoC) facilitates hardware-based data protection for increased SoC reliability and functional safety. Source: Arteris IP

One crucial technology effort is the resilient interconnect IP that is tolerant of errors due to environmental radiation and manufacturing defects. This is important to the overall autonomous vehicle system because the on-chip interconnect “sees” all the data traffic on an SoC and can correct this data or warn of uncorrectable errors in real time. Ensuring that functional safety is implemented for an entire system requires significant investment by not only the automotive semiconductor companies, but also their semiconductor IP providers who provide the means to increase system performance and safety. And the on-chip interconnect is an important control point for ensuring SoC-wide functional safety.

Interconnect IP a key enabler
As the amount of electronic content in vehicles increases, semiconductor devices are becoming more complex and more valuable. This will provide many more years of potential innovation and growth for the semiconductor industry. Automotive is now and will continue to be the fastest growing market for the semiconductor industry, although mobility will continue as the largest market from a unit volume standpoint.

For autonomous vehicle systems, the SoC architecture is the innovation control point for enabling the massive power-efficient processing gains required to control these systems in a safe manner. All the software in the world is fruitless until chip engineers tackle these hardware challenges. While there are many opportunities for innovation in this segment, we need to move further toward a fault-tolerant interconnect that adapts in the field to changing conditions. This technology is foundational to everything else.

As an experienced and pioneering IP provider, Arteris IP has contributed to the innovation in the SoC designs that are the “brains” of today’s ADAS systems and semi-autonomous vehicle systems. Arteris SoC interconnect IP has been integrated into several autonomous driving designs that are now in production for passenger vehicles and provides functional safety features that help automotive Tier-1s and OEMs more easily achieve ISO 26262 compliance.

If you’re driving a recent model Tesla, Volvo, Mercedes, BMW, Nissan, GM, Volkswagen or Audi that has ADAS or autonomous driving capabilities, then our technology is under the hood. The key to the future of autonomous driving systems is to add even more performance and safety features to the SoCs within these systems and to implement them at the lowest possible level, the on-chip interconnect.

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