Why Is Semiconductor Schedule Predictability Boring?


Why is it not sexy to talk about the manageability of system-on-chip (SoC) projects? As an IP vendor, we are constantly bombarded with questions about how our technology can enhance performance, reduce latency, and lower power consumption. At the same time, reducing cost and time to market for the SoC design conflict with these requirements, even though they rank right up there among the top en... » read more

CPU, GPU or … VPU?


Where is the semiconductor industry going in the post-smartphone era? What trends are going to shape next-generation applications and SoC development? Just by walking around the CES show floor this year, I would say advanced visual processing technology is the horse to put money on. It was everywhere, from ADAS systems, drones, to GoPro cameras, IP cameras with embedded facial recognition, m... » read more

How To Reduce Timing Closure Headaches


As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

Top 5 Reasons The SoC Interconnect Matters


The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

ISO 26262: Top 3 Reasons For Hardware Implementation Of Functional Safety


I’ve written articles before about ISO 26262 Certification because many SoC design teams are challenged by the barriers they have to overcome to achieve automotive functional safety, especially if they previously enjoyed success in mobility or computing but now want to shift attention to the growing array of electronics used in transportation such as automated driver assistance systems (ADAS)... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency


Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

7 Ways to Assess Semiconductor IP Quality


Design teams today are struggling with the quality of semiconductor intellectual property. These teams want first-pass success for SoC creation, but that is becoming increasingly difficult to achieve—especially with highly configurable IP. Yet the more configurable the IP is, the more desirable it is as a differentiator. And if not developed correctly, it may be even more risky than non-confi... » read more

Tear Down The Wall Between Front-End And Back-End Teams


As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

Tear Down The Wall Between Front-End And Back-End Teams


Because system-on-chip devices are increasingly complex, it is becoming imperative for design teams and organizations to reexamine how they work with one another in order to innovate new ways to improve productivity in delivering devices to market. The area that could benefit most is the divide that separates the semiconductor front-end design process from the physical back-end design process. ... » read more

Focus More Attention On The SoC’s Central Nervous System


In multiple conversations over the years, I’ve often compared the interconnect fabric within SoC designs to the central nervous system of the human body. The point that I try to make is that the potential of the SoC’s performance and functionality is tied to the information that travels through the fabric and interconnect to all the on-chip IP components. Improving a chip’s ability to com... » read more

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