Reducing Latency In ADAS SoC Design Enhances QoS For Digital Mirroring

How interconnect IP enables a new side view mirror technology.


The state-of-the-art of Advanced Driver Assistance Systems (ADAS) is quickly changing, and ADAS chip engineers are finding that on-chip quality-of-service (QoS) is becoming a system-level constraint on ADAS performance. Designers need innovative approaches to address these issues, which is why Dream Chip Technologies highlighted one such method in a recent presentation.

Dream Chip Technologies (DCT) is using ArterisIP FlexNoC interconnect IP plus Resiliency for functional safety for its highly anticipated ADAS reference design, which has been developed as part of a European Union-funded automotive SoC project. Dream Chip featured this design in April at the “FD-SOI Symposium” event, organized in Silicon Valley by the SOI Consortium. This innovative approach earned a recap in a blog on the show’s featured developments.  See the “And Much More” section of the story to learn more about the companies participating in this project.

ArterisIP is a valuable contributor to this highly anticipated design because DCT it is tackling a new technical challenge with this system – replacing a car’s side view mirrors with video screens fed by multiple cameras. The new feature is called “digital mirroring.” The problem? As the FD-SOI article states, “Why hasn’t this been done before? Because LED flickering really messes with sensor readings.”

This Dream Chip Technologies digram shows the ADAS functional flow for image sensor processing, including the different processing elements and hardware accelerators that perform specific functions. The challenge is that these elements must share high-bandwidth data streams at low latencies to meet near-real time deadline.

When ArterisIP engineers first met the Dream Chip design team, we set out to address the QoS challenges associated with ADAS digital mirroring. Additional algorithms are required to deal with LED flickering, and the challenge is to execute these in parallel with other functionality without affecting bandwidth needs or time constraints for these functions. In particular, the digital mirroring algorithms require very high bandwidth on-chip communications while meeting tight latency schedules for some of the on-chip traffic. It turns out that FlexNoC IP plus Resiliency and Functional Safety was tremendously helpful to Dream Chip in this regard.

Dream Chip uses ArterisIP for on-chip networking and implements a concept called Forward Body Bias (FBB) to allow for faster-switching transistors. There are many items in ADAS systems that require stringent QoS, and ArterisIP’s FlexNoC interconnect IP helps designers achieve this by increasing bandwidth and reducing latency in the communication paths between different SoC subsystems. As for Dream Chip’s design, Arteris FlexNoC IP interconnect not only helps with the specific functionality of digital mirroring, it also serves as the backbone of the entire chip.

Dream Chip SoC block diagram (with the functional IP blocks highlighted) uses interconnect IP to address system-level issues of latency and Quality of Service.

Progress is being made quickly in our industry around ADAS and autonomous driving: Dream Chip licensed the FlexNoC interconnect IP in May 2016 and by February 2017 was demonstrating a working ADAS reference design platform at Mobile World Congress! Now the chips are already being used in automotive reference design systems. Also, the European Commission is evaluating this design under the purview of the ENIAC THINGS2DO reference development platform program. If successful, this effort could be licensed to several international automotive system suppliers.

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