category: Blogs – SLD

category: IoT, Security & Automotive

Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction Results
By Yousry ElMaghraby - 20 Dec, 2018 - Comments: 0

There comes a time at every foundry and IC design company when it becomes necessary to run a correlation between a rule-based parasitic extraction (PEX) table and a field solver solution. And when that time arrives, there are a few (five, to be precise) details that will help ensure the correlation produces accurate results. But before we get to those, let’s do a quick refresh on PEX techniqu... » read more

Beyond The RISC-V ISA
By Gajinder Panesar - 20 Dec, 2018 - Comments: 1

For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

Verification Throughput Is Set To Increase By Leaps And Bounds In 2019
By Frank Schirrmeister - 20 Dec, 2018 - Comments: 0

In June 2015, I wrote the blog “Towards A Metric To Measure Verification Computing Efficiency” that introduced what we now refer to here at Cadence as the “productivity wheel” for verification payloads—the sequence of “build”, “allocate”, “run” and “debug” that is repeated thousands of times during a project. It was meant to set up the launch of the Palladium Z1 platfo... » read more

Deep Learning Hardware: FPGA vs. GPU
By Farhad Fallahlalehzari - 20 Dec, 2018 - Comments: 0

FPGAs or GPUs, that is the question. Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer a HW platform that runs computationally intensive machine learning algorithms fast and efficiently. As Deep Learning has driven most of the advanced machine learning applications, it is r... » read more

Compute And AI In Next-Generation SSD Designs
By Mike Thompson - 20 Dec, 2018 - Comments: 0

Over the last 40 years digital storage has advanced at an amazing rate. Because it operates out of sight digital storage tends to be taken for granted, but today there is more storage capacity in the devices in our pockets than what existed in mainframe computers 30 years ago. With the rise of artificial intelligence (AI) this trend will continue and the results will be nothing less than astoun... » read more

The Fibonacci Calculator
By Sergio Marchese - 20 Dec, 2018 - Comments: 0

The holiday season is all about traditions, and the annual holiday puzzle has become a tradition here at OneSpin. Two years ago, we challenged engineers everywhere to solve the famous Einstein’s Riddle using a formal tool. We received some interesting solutions. Last year, we drew an even bigger response to our invitation to tackle the “World’s Hardest Sudoku.” These puzzles are fun, of... » read more

Heterogeneous Computing Raises The Bar For Functional Verification
By Raik Brinkmann - 29 Nov, 2018 - Comments: 0

If there’s one thing certain in chip development, it’s that every innovation in architecture or semiconductor technology puts more pressure on the functional verification process. The increase in gate count for each new technology node stresses tool capacity. Every step up in complexity makes it harder to find deep, corner-case bugs. The dramatic growth in SoC designs brings software into p... » read more

Virtual Design Chains At The EDA Forum
By Frank Schirrmeister - 29 Nov, 2018 - Comments: 0

The German edacentrum’s EDA Forum was held in Berlin, Germany, in early November. It was very interesting to see the design chain effects in the automotive domain, very visible in a panel yours truly was part of, together with Audi, Bosch, Infineon, MicroChip, Synopsys, Mentor, and the BMBF. Driven from the top of the design chain, the direction is clearly to go more virtual to optimize the c... » read more

Physical Verification In The Cloud
By Manoz Palaparthi - 29 Nov, 2018 - Comments: 0

Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool ... » read more

Supercomputers Are For Everyone
By Mike Gianfagna - 29 Nov, 2018 - Comments: 0

Our SerDes world tour continues. This past month, we demonstrated our 7nm 56G long-reach SerDes in Dallas and Israel. In Dallas, our demonstration included error-free operation in 56G PAM4 over a 30dB channel without forward error correction through an eye-popping five-meter cable. Many thanks to our partner Samtec for providing that cable, allowing backplane designers to now “reach beyond th... » read more

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