category: Blogs – SLD

category: IoT, Security & Automotive

The Revenge Of The Digital Twins
By Frank Schirrmeister - 27 Sep, 2018 - Comments: 0

How do we verify artificial intelligence? Even before “smart digital twins” get as advanced as shown in science fiction shows, making sure they are “on our side” and don’t “go rogue” will become a true verification problem. There are some immediate tasks the industry is working on—like functional safety and security—but new verification challenges loom on the horizon. As in pr... » read more

Giving Cars A Bird’s-Eye View
By Farhad Fallahlalehzari - 27 Sep, 2018 - Comments: 0

Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable of human transportation was built in 1769 [1]! As a person who likes driving, I wouldn’t like to have a ‘fully’ autonomous car, but I would like to get some assistanc... » read more

56G 7nm SerDes: Eyewitness Account
By Mike Gianfagna - 27 Sep, 2018 - Comments: 0

High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our... » read more

It’s All About Staying Ahead Of The Test Challenges Curve
By Steve Pateras - 11 Sep, 2018 - Comments: 0

Since the early days when semiconductor devices contained a mere handful of gates, the manufacturing test world has been focused on how to detect the greatest number of potential defects in the shortest amount of time. This fundamental goal has not changed over the years and continues at 5nm and beyond. What has dramatically changed over the years, however, is the variety of techniques used ... » read more

A Primer On Last-Level Cache Memory For SoC Designs
By Kurt Shuler - 06 Sep, 2018 - Comments: 0

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver assistance systems (ADAS), machine learning, and data-center applications. LLC is a standalone memory that inserts cache between functional blocks and external memory to ease conflicting requireme... » read more

Digital IC Bring-Up With A Bench-Top Environment
By Matthew Knowles - 23 Aug, 2018 - Comments: 1

One of the hottest markets for IC today is artificial intelligence (AI). The designs for AI chips are also among the largest and most complex, with billions of transistors, thousands of memory instances, and complex design-for-test (DFT) implementations with unique bring up and debug requirements. At this point, the volume of new AI chips is relatively low, but time-to-market is of paramount im... » read more

Demystifying EDA Support For ISO 26262 Tool Qualification
By Sergio Marchese - 23 Aug, 2018 - Comments: 0

My new, mid-size car is equipped with many advanced driver-assistance systems. To be honest, it’s taking me time to get used to some of them, as, for example, lane-centering assist that seamlessly takes control of my steering wheel. However, I cannot wait to get my hands off a fully autonomous vehicle and be able to take a nap while 7nm chips run machine learning and other artificial intellig... » read more

Verification Trends Enabling A 5G Future
By Frank Schirrmeister - 23 Aug, 2018 - Comments: 0

Applications have driven requirements for verification for quite some time now, as I have written previously regarding Aero & Defense, AI and Machine Learning and the Internet of Things. In wireless communication, we are just at the brink of the transition to Fifth Generation Networks, or 5G. This transition will not only lead to new applications and use models that will impact our day-to-d... » read more

Is Synthesis Still Process-Independent?
By Bernadette Mortell - 23 Aug, 2018 - Comments: 0

For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion. With the arrival of physical synthesis, physical effects could be taken into consideration in... » read more

Accessing Registers With UVM-RAL
By Sunil Sahoo - 23 Aug, 2018 - Comments: 0

As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it and each field can represent a particular feature that can be configured. The device then reads that register and uses that information to change settings or modes... » read more

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