Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

By Vineet Pancholi - 21 Nov, 2024 - Comments: 0

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

HBM Options Increase As AI Demand Soars

By Laura Peters - 21 Nov, 2024 - Comments: 0

High-bandwidth memory (HBM) sales are spiking as the amount of data that needs to be processed quickly by state-of-the-art AI accelerators, graphic processing units, and high-performance computing applications continues to explode. HBM inventories are sold out, driven by massive efforts and investments in developing and improving large language models such as ChatGPT. HBM is the memory of ch... » read more

Using Dummy Patterning To Solve Etch Uniformity Problems

By James Kim - 21 Nov, 2024 - Comments: 0

Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes. Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especi... » read more

Luminary Panel Sees Progress In EUV Pellicle Adoption As Critical For EUV

By Jan Willis - 21 Nov, 2024 - Comments: 0

A significant focus of the 2024 SPIE Photomask and EUV conference was on EUV lithography and high-numerical-aperture (high-NA) EUV lithography, offering the potential to drive resolution to new heights. These EUV solutions bring new challenges such as pellicles, mask inspection, and smaller and smaller minimum mask dimensions. Progress has been impressive, according to lithography luminary Dr. ... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging

By Gregory Haley - 21 Nov, 2024 - Comments: 0

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

Package Assembly Design Kits (PADK) Benefits For Packaging Design Engineers

By Amkor - 21 Nov, 2024 - Comments: 0

A new IEEE technical paper titled "Package Assembly Design Kits (PADK's)- The Future of Advanced Wafer-Level Manufacturing" was written by researchers from Amkor. Find the technical paper here. September 2024. "Although package design and IC design are two different worlds, they share several key similarities that have contributed to the successful use of Package Assembly Design Kits (PAD... » read more

Tradeoffs In Leading-Edge Chip Design

By Katherine Derbyshire - 21 Nov, 2024 - Comments: 0

Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available? Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet eve... » read more

The State Of The EDA Industry In 2024

By Bob Smith - 21 Nov, 2024 - Comments: 0

In what has become a yearly custom, I recently spoke to Jay Vleeschhouwer, Managing Director of Griffin Securities, for an update on his view of the state of the electronic design automation (EDA) industry. My inquiries were based on his presentation at the 2024 Design Automation Conference (DAC). With his long background as an informed EDA industry follower, I knew it would be an enlightening ... » read more

One Chip Vs. Many Chiplets

By Ed Sperling - 20 Nov, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the growing list of challenges at advanced nodes and in advanced packages, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Ponnusw... » read more

Asia Government Funding Surges

By Liz Allan - 18 Nov, 2024 - Comments: 0

Billions of dollars have been pouring into Asian countries for the past few years in an effort to boost their production capacity, explore leading-edge technology, compete on the global stage, and shore up supply chains in the face of geopolitical turmoil. Each country has its own plan to maintain a foothold in the global market, from China’s Big Fund to Korea’s Yongin Cluster and Japan�... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: Manufacturing, Packaging and Materials

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