Using TCAD To Simulate Wide-Bandgap Materials For Electronics Design

By Shela Aboud - 22 Jan, 2024 - Comments: 0

Wide-bandgap (WBG) semiconductors are a class of materials that can offer a range of advantages over silicon. These materials can operate at higher voltages and higher temperatures, serving as critical enablers of innovation in Power and RF applications and functioning in a wider range of environments that are sometimes extreme. Electronics applications benefit from these wide-bandgap materials... » read more

Elimination Of Die-Pop Defect By Vacuum Reflow For Ultrathin Die With Warpage In Semiconductor Packaging Assembly

By Amkor - 18 Jan, 2024 - Comments: 0

Semiconductor die thickness is getting thinner over time due to improvement of power efficiency in advance power electronic packages. Ultrathin die with convex warpage can easily deteriorate the solder void removal process during solder reflow, leading to various packaging reliability issues. In particular, a new type of packaging defect phenomenon—die-pop—is observed. Vacuum reflow process... » read more

Electromigration Performance Of Fine-Line Cu Redistribution Layer (RDL) For HDFO Packaging

By JiHye Kwon - 18 Jan, 2024 - Comments: 1

The downsizing trend of devices gives rise to continuous demands of increasing input/output (I/O) and circuit density, and these needs encourage the development of a High-Density Fan-Out (HDFO) package with fine copper (Cu) redistribution layer (RDL). For mobile and networking application with high performance, HDFO is an emerging solution because aggressive design rules can be applied to HDFO ... » read more

Many More Hurdles In Heterogeneous Integration

By Laura Peters - 18 Jan, 2024 - Comments: 0

Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Navigating Heat In Advanced Packaging

By Gregory Haley - 18 Jan, 2024 - Comments: 0

The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications

By Brett Lowe - 18 Jan, 2024 - Comments: 0

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

AI-Driven Innovation For Manufacturing Automation

By Calvin Shiao - 18 Jan, 2024 - Comments: 0

By Calvin Shiao, AshtonWS Huang, and Alfos Hsu Artificial intelligence (AI) is changing the world and improving our lives in many ways. The semiconductor industry is a key part of the AI revolution, as it provides powerful computing chips for AI applications and leverages AI to optimize business operations and management, customer service, office workflows, as well as the intricate realms of... » read more

Photonic Debonding Provides A Cost-Efficient, High-Throughput Debond Process

By Jessica Albright - 18 Jan, 2024 - Comments: 0

As emerging technologies require ultrathinned device wafers, traditional debonding processes can pose some challenges. Photonic debonding is an innovative debonding process utilizing a carrier coated with an inorganic metal release layer that aids in the release of the thinned wafer from the carrier substrate with no force and no damage to the delicate wafer upon activation of the release layer... » read more

Semiconductors Accelerate The Artificial Intelligence Revolution

By Ajit Manocha - 18 Jan, 2024 - Comments: 0

By Ajit Manocha, Pushkar Apte, and Melissa Grupen-Shemansky Five years ago, SEMI published an article predicting that Artificial Intelligence (AI) would change everything – and it has! AI has moved out of labs and taken popular imagination by storm. It is now a hot topic of discussion everywhere, from family dining tables and corporate boardrooms to corridors of government. While it m... » read more

An Efficient, Cost-Effective, Continuous Polymer Purification Method

By Brewer Science - 18 Jan, 2024 - Comments: 0

Polymer precipitation is a crucial process in chemical engineering and is widely applicable to many industries including semiconductors, pharmaceuticals, and wastewater treatment. In many industries, batch polymer precipitation is a common technique for polymer purification. However, batch polymer precipitation is an arduous and inefficient process, which generates excess solvent waste. It is l... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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