The Pitfalls Of Auto-Stitching In Double-Patterning


Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Design Process Technology Co-Optimization For Manufacturability


Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more

Mask Maker Worries Grow


Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Sorting Out Next-Gen Memory


In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

Deploying Multi-Beam Mask Writers


Elmar Platzgummer, chief executive of IMS Nanofabrication, sat down with Semiconductor Engineering to discuss the company’s deal with Intel, photomasks, multi-beam mask writer technology and other topics. What follows are excerpts of that conversation. SE: This has been a significant year for IMS for two reasons. First, Intel recently announced plans to acquire IMS. Second, at the recent ... » read more

NextFlex Takes High Profile With Events And First Round Of Project Announcements


NextFlex, FlexTech’s flexible hybrid electronics (FHE) manufacturing institute, has been headlining flexible electronics in a major way in the past few weeks. From hosting contingents from the White House and the Pentagon, Members of Congress and local dignitaries, to announcing new development projects and partners, this one-year old organization is off to a rapid start while highlighting ad... » read more

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography


Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

Envelope Tracking Fundamentals And Test Solutions?


There was once a time when your cell phone could go for days without needing to be recharged. Today, despite the innovations in cell phone battery technology, new demands, such as more internal radios and larger and higher resolution screens, place a greater drain on battery life than ever before. As a result, engineers must consistently innovate to reduce the power consumption as new technolog... » read more

Device Overlay Method For High-Volume Manufacturing


By Honggoo Lee, Sangjun Hana and Youngsik Kima of SK Hynix; Myoungsoo Kim, of the Department of Semiconductor System Engineering at Korea University; Hoyoung Heo, Sanghuck Jeon and DongSub Choi, KLA-Tencor Korea; and Jeremy Nabeth, Irina Brinster, Bill Pierson, and John C. Robinson of KLA-Tencor. Abstract Advancing technology nodes with smaller process margins require improved photolithogra... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

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