Fins And Wires – How Do We Get To 5nm?


As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON... » read more

How Small Will Transistors Go?


By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

Device Pin-Specific Property Extraction For Layout Simulation


As we work through the sub-20 nm design space, the interactions between and effects on devices that are near each other are becoming critical factors in achieving the desired electrical performance. Accurate extraction of device pin-specific properties for modelling these effects is essential to attaining design goals. LVS extraction challenges Layout vs. schematic (LVS) comparison tools prov... » read more

China’s Capital Equipment Market To Boom


The worldwide semiconductor capital equipment market declined 3% last year to $36.53 billion from 2014’s $37.5 billion, but inside China the story was significantly different. Capital equipment sales there increased by 12% in 2015, to $4.9 billion. In fact, only Japan showed a higher growth rate last year, of 31%, according to figures from [getentity id="22821" comment="SEMI"] and the Semi... » read more

Making Phones Better


Beneath a smartphone's slick packaging is some interesting, highly sophisticated technology that makes the user experience what it is today. Much of that experience relies on satisfying our ever growing desire for more data capacity for video, social media and the like. Providing that capacity relies on robust filtering to receive just your data stream amongst many nearby other streams. But tha... » read more

Are We Looking At The IoT Through Rose-Colored Glasses?


There’s been a lot of anticipation and promise associated with the explosive growth expected from the deployment of the Internet of Things. The prospect of 30 billion to 50 billion connected devices and all the associated electronics brings rosy visions of a return to double-digit semiconductor industry growth rates. Let’s take a look at the realities of the impending impact. MEMS, ... » read more

From Uncertainty To New Markets


The 11th annual SEMI/Gartner Market Symposium at SEMICON West 2016 presented diverse perspectives on trends and developments in the macroeconomic environment as well as the semiconductor manufacturing supply chain. The themes have significant and immediate impact on the industry and include economic uncertainty, Brexit, China’s ambitious plans for an indigenous chip industry, and evolving end... » read more

Mask Maker Worries Grow


Leading-edge photomask makers face a multitude of challenges as they migrate from the 14nm node and beyond. Mask making is becoming more challenging and expensive at each node on at least two fronts. On one front, mask makers must continue to invest in the development of traditional optical masks at advanced nodes. On another front, several photomask vendors are preparing for the possible ra... » read more

What Transistors Will Look Like At 5nm


Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

Optical Metrology Solutions For 10nm Films Process Control Challenges


By Sridhar Mahendrakar (a), Alok Vaida (a), Kartik Venkataraman (b), Michael Lenahan (a), Steven Seipp (a), Fang Fanga (a), Shweta Saxena (a), Dawei Hu (b), Nam Hee Yoon (b), Da Song (b), Janay Camp (b), Zhou Ren (b). [a: GlobalFoundries; b:KLA-Tencor] Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets r... » read more

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