category: News

category: IoT, Security & Automotive

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2023 - Comments: 0

Cadence's Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost. Synopsys' Kiran Vittal considers the driving factors behind RISC-V's growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers. Siemens... » read more

Chip Industry Week In Review
By The SE Staff - 01 Dec, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

Blog Review: November 29
By Jesse Allen - 29 Nov, 2023 - Comments: 0

Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

Chip Industry Week In Review
By The SE Staff - 22 Nov, 2023 - Comments: 0

By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Chip Industry Week In Review
By The SE Staff - 17 Nov, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Blog Review: November 15
By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

Chip Industry Week In Review
By The SE Staff - 10 Nov, 2023 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Bosch, Infineon, and NXP were cleared in Germany to each acquire 10% of the European Semiconductor Manufacturing Co. (ESMC), established by TSMC, solidifying the supply chain against future shortages, particularly for automotive chips. “ESMC intends to build and operate another large semiconductor factory in Dresden, in which the three Europ... » read more

Blog Review: Nov. 8
By Jesse Allen - 08 Nov, 2023 - Comments: 0

Siemens' Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance. Synopsys' William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy... » read more

Chip Industry Week In Review
By The SE Staff - 03 Nov, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Blog Review: November 1
By Jesse Allen - 01 Nov, 2023 - Comments: 0

Cadence’s Rich Chang finds that although UVM has being used for testbench creation for more than a decade, it is still challenging to debug problems that are inside of UVM testbench. Siemens’ Keith Felton suggests that early analysis in complex advanced packaging flows can enable designers to spot potential issues early to avoid built-in constructs that cause design failures and require ... » read more

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