Blog Review: Jan. 8


Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

Chip Industry Week in Review


Lawrence Livermore National Laboratory is ramping up R&D for next-gen EUV and plasma-based particle sources, aiming to increase the EUV laser source power by an order of magnitude while also making it more energy-efficient. Specifically, the goal is to replace today's CO2-based laser with a solid-state laser, using a thulium-doped yttrium lithium fluoride medium to increase the laser's powe... » read more

Chip Industry Week In Review


Updated for 12/20 government fundings and 12/23 for China trade investigation announcements. President Biden announced a trade investigation into "China's unfair trade practices in the semiconductor sector."  The announcement stated "PRC semiconductors often enter the U.S. market as a component of finished goods. This Section 301 investigation will examine a broad range of the PRC’s non-m... » read more

Blog Review: Dec. 18


Siemens’ Michael Munsey predicts that the convergence of AI, advanced packaging, and rise of software-defined products aren’t just incremental changes but will represent a fundamental shift in how we think about semiconductor design and manufacturing. Cadence's Veena Parthan points to hex-core voxels as a significant leap forward for the CFD meshing process that blends the best of struct... » read more

Chip Industry Week In Review


The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Chip Industry Week In Review


Global chips sales hit a record $56.9 billion in October, a 22% increase versus October 2023, according to the Semiconductor Industry Association. Also, global semiconductor equipment billings reached $30.38 billion in Q3 2024, a 19% YoY increase and 13% growth QoQ, SEMI reported. TSMC commenced equipment installation for its 2nm fab in Kaohsiung, Taiwan, six months ahead of schedule. The 2n... » read more

Blog Review: Dec. 4


Siemens' Reetika explains how creating and verifying a complete reset tree structure allows designers to trace the flow of reset signals across the design and ensure that every sequential element is tagged correctly within its respective reset domain. Cadence's Durlov Khan suggests DDR5 DIMM Memory Models and Discrete Component Models as part of a flexible approach to validating specific com... » read more

Chip Industry Week In Review


Intel CEO Pat Gelsinger retired on Dec. 1, according to the company. He will be replaced by two interim co-CEOs, David Zinsner, who also continues to serve as CFO  and Michelle Johnston Holthaus, who has been named CEO of Intel Products. In addition, Frank Yeary was named interim executive chairman. Intel has been under pressure investors as non-traditional rivals, including Arm and NVIDIA, co... » read more

Chip Industry Week In Review


SK hynix started mass production of 1-terabit  321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese government beginning in fiscal year 2025, reports Nikkei. This is on top of ¥920 billion yen ($5.98B) Rapidus has already received from the government in support of its goal to reach commer... » read more

Blog Review: Nov. 20


Siemens’ Jonathan Muirhead explains why matching and symmetry are so important for analog and RF circuits, especially in topological structures like differential pairs and current mirrors, and introduces checking techniques to ensure compliance. Cadence's Satish Kumar Padhi examines the significance of randomization in PCIe IDE verification, focusing on how it ensures data integrity and en... » read more

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