Where Advanced Packaging Makes Sense

By Ed Sperling - 10 Dec, 2018 - Comments: 0

Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

IP Tracking and Management

By Brian Bailey - 29 Nov, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss IP tracking and management with Ranjit Adhikary, VP of marketing for ClioSoft; Jim Bruister, director digital systems (since retired) at Silvaco; Marc Greenberg, product marketing group director at Cadence; and Kelvin Low, VP of Marketing at Arm. What follows are excerpts from that conversation. SE: What is the scope of the problem? What are ... » read more

Machine Learning Moves Into Fab And Mask Shop

By Mark LaPedus - 14 Nov, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss artificial intelligence (AI), machine learning, and chip and photomask manufacturing technologies with Aki Fujimura, chief executive of D2S; Jerry Chen, business and ecosystem development manager at Nvidia; Noriaki Nakayamada, senior technologist at NuFlare; and Mikael Wahlsten, director and product area manager at Mycronic. What follows are excerpt... » read more

The Impact of Domain Crossing on Safety

By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Machine Learning Invades IC Production

By Mark LaPedus - 18 Oct, 2018 - Comments: 0

So Many Waivers Hiding Issues

By Brian Bailey - 05 Oct, 2018 - Comments: 0

Domain Crossing Nightmares

By Brian Bailey - 27 Sep, 2018 - Comments: 1

Aging In Advanced Nodes

By Ann Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Sorting Out Packaging Options

By Ed Sperling - 10 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Butler, executive vice president and general manager of SPTS Technologies; Ingu Yin Chang, senior vice president president at ASE Group; Hubert Karl Lakner, executive director of the Fraunhofer Institute for Photonic Microsystems; Robert Lo, division director for electronics and optoelectronics research at Industrial Te... » read more

Using More Verification Cores

By Brian Bailey - 30 Aug, 2018 - Comments: 1

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

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Where Advanced Packaging Makes Sense

IP Tracking and Management

Machine Learning Moves Into Fab And Mask Shop

The Impact of Domain Crossing on Safety

Machine Learning Invades IC Production

So Many Waivers Hiding Issues

Domain Crossing Nightmares

Aging In Advanced Nodes

Sorting Out Packaging Options

Using More Verification Cores

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